Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

• US 8,832,403 B2
• Filed: 06/08/2010
• Issued: 09/09/2014
• Est. Priority Date: 11/13/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ohmacht, Martin
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): GOLDSCHMIDT, CRAIG S
• Application Number:
  US12/796,411
• Publication Number:
  US 20110119470A1
• Time in Patent Office: 1,554 Days
• Field of Search: 711/167
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Claims

1. A multiprocessor system adapted to carry out parallel threads of instructions and comprising:

a plurality of processors and a memory device coupled to the processors;

a plurality of messaging units for issuing and queuing memory access requests associated with the memory device; and

a central synchronization controller communicating synchronization control information to or from the messaging units via point to point communication rather than via a bus, the synchronization control information including independently operable instructions which comprises;

a first instruction and a second instruction;

one or more of the plurality of processors issuing memory write commands;

the central synchronization controller issuing the first instruction after the issuance of the memory write commands, wherein before the issuance of the first instruction, the issued memory write commands are not visible to all the plurality of processors, wherein after the issuance of the first instruction, the issued memory write commands are visible to all the plurality of processors; and

the central synchronization controller issuing the second instruction which enables a data location update of the memory device and a guard (flag) location update of the memory device to be performed at separate times by the one or more of the plurality of processors.

2. The system of claim 1, wherein

the messaging units queuing memory requests comprise:

a plurality of prefetch units and a plurality of data caches; and

the system comprises;

facilities receiving information regarding the memory requests being queued and supporting generation completion detection.

3. A multiprocessor system adapted to carry out parallel threads of instructions and comprising:

a plurality of processors and at least one memory device coupled to the processors;

a plurality of messaging units for issuing and queuing memory access requests; and

a central synchronization controller supplying a generation tag to the memory access requests and communicating synchronization control information to or from the messaging units via point to point communication rather than via a bus, the synchronization control information including independently operable instructions which comprises;

a first instruction and a second instruction

one or more of the plurality of processors issuing memory write commands;

the central synchronization controller issuing the first instruction after the issuance of the memory write commands, wherein before the issuance of the first instruction, the issued memory write commands are not visible to all the plurality of processors, wherein after the issuance of the first instruction, the issued memory write commands are visible to all the plurality of processors; and

the central synchronization controller issuing the second instruction which enables a data location update of the memory device and a guard (flag) location update of the memory device to be performed at separate times by the one or more of the plurality of processors.

4. The system of claim 3, wherein the system comprises:

the plurality of processors for carrying out the threads, and at least one of the threads includes a memory synchronization instruction which includes the synchronization control information; and

the central synchronization controller incrementing a central generation counter responsive to the memory synchronization instruction.

5. The system of claim 3, wherein the central generation controller comprises a wrapping generation counter and a wrapping reclaim pointer that cannot pass each other.

6. The system of claim 5, wherein generation completion is detected responsive to the reclaim pointer.

7. The system of claim 3, wherein the units comprise a plurality of processing cores, a plurality of prefetch units, and a plurality of data caches.

8. The system of claim 3, wherein the units queuing memory access requests comprise one or more of:

at least one supplementary processing and prefetch unit;

at least one L2 cache;

at least one direct memory access unit; and

at least one peripheral component interconnect express unit; and

the system comprises;

facilities receiving information regarding the memory requests being queued and supporting generation completion detection.

9. The system of claim 8, wherein each unit queuing memory access requests produces an indication of generations of memory accesses in flight within that unit.

10. The system of claim 9, wherein the indication is a vector with a bit for each generation.

11. The system of claim 10, wherein the facilities comprise an OR reduce tree that receives and combines the vectors from the units queuing memory access requests to yield a global indication of generations of memory accesses in flight.

12. The system of claim 11, comprising:

a plurality of interface units receiving and processing at least one output responsive to the tree and treating a memory access request as completed responsive to the output indicating that a tagging result associated with the request is no longer in flight in the system.

13. The system of claim 3, comprising:

the plurality of processors issuing memory synchronization instructions which includes the synchronization control information and wherein the system tags concurrent memory access requests with a same generation number, responsive to the synchronization controller.

14. The system of claim 3, wherein

the synchronization controller comprises:

a generation counter;

a reclaim pointer; and

a broadcast facility broadcasting values of the generation counter and the reclaim pointer to at least some of the units; and

at least one of the messaging units comprises an interface unit requesting a new generation responsive to the memory synchronization instruction; and

the generation controller incrementing the generation counter responsive to the interface unit and relative positions of the reclaim pointer and generation counter.

15. The system of claim 3, comprising:

the plurality of processors issuing memory synchronization requests; and

a plurality of detectors, coupled with the processors;

detecting generations of instructions issued by the processors; and

recording whether generations associated with the instructions are completed.

16. The system of claim 15, comprising:

an interface unit that includes the detectors, the interface unit aggregating concurrent synchronization requests from a plurality of threads requesting a new generation receiving a common generation indication for the concurrent synchronization requests notifying threads of generation completion.

17. The system according to claim 3, wherein the independently operable instructions further include a third instruction, the third instruction setting up a barrier which is configured to attempt to render visible a value, which the third instruction accessed prior to an issuance of a memory store operation, to all the plurality of processors.