Retrieving boot instructions from nonvolatile memory

• US 8,832,423 B2
• Filed: 09/10/2013
• Issued: 09/09/2014
• Est. Priority Date: 04/10/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wu, Stephen
• Primary Examiner(s): Cao, Chun
• Application Number:
  US14/022,576
• Publication Number:
  US 20140013097A1
• Time in Patent Office: 364 Days
• Field of Search: 713/1, 713/2
• US Class Current: 713/2
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/44573 Execute-in-place [XIP]

Abstract

Systems and processes for booting a device can be implemented by detecting a reset signal associated with the device and retrieving a predetermined page of data from a nonvolatile memory location into a register associated with the nonvolatile memory. The nonvolatile memory may be designed and implemented such that each page of data is retrieved from the nonvolatile memory as a unit, and the page of data includes instructions for use in booting the device. A command to read data stored in the register is received, and the command can include an address identifying a location of one or more instructions within the register. In response, the one or more instructions are retrieved from the register for execution by a processor.

Claims

1. A method for booting a computing device, the method comprising:

detecting a reset signal associated with the computing device; and

in response to detecting the reset signal;

retrieving, by an internal controller that is a part of a non-volatile memory apparatus, a predetermined page of data from a location in the non-volatile memory apparatus, wherein each page of data is retrieved from the non-volatile memory as a unit and the predetermined page of data includes at least one instruction for booting the device;

loading, by the internal controller, the pre-determined page of data including the at least one booting instruction into a register associated with the non-volatile memory apparatus;

receiving, by the internal controller, a command from a host processor coupled to the non-volatile memory apparatus to read data stored in the register, wherein the command includes an address identifying a location within the register of the at least one booting instruction;

retrieving the at least one instruction from the register by the internal controller;

transmitting the at least one instruction from the internal controller to the host processor without storing the data in another memory.

2. The method of claim 1, the non-volatile memory comprises a NAND flash memory.

3. The method of claim 1, wherein retrieving a pre-determined page of data is performed automatically in response to detecting the reset signal.

4. The method of claim 1, further comprising receiving a plurality of commands to read data stored in the register, wherein the data read in response to the plurality of commands comprises code for loading separate boot loader code to a random access memory associated with the processor.

5. The method of claim 4, wherein the separate boot loader code is configured for loading operating system or application code from the non-volatile memory to the random access memory.

6. The method of claim 1, wherein the non-volatile memory is configured to enable random access to any byte in the register in response to a command to read data stored in the register.

7. The method of claim 1, further comprising converting an instruction fetch command from the processor into at least one command to read data stored in the register.

8. A computer-accessible non-transitory storage medium having program instructions therein that, in response to execution by a system, cause the system to perform operations comprising:

detecting a reset signal associated with the system; and

in response to detecting the reset signal;

retrieving a pre-determined page of data from a location in a non-volatile memory device by an internal controller included in the non-volatile memory device, wherein each page of data is retrieved from the non-volatile memory as a unit and the pre-determined page of data includes at least one instruction for booting the system;

loading, by the internal controller, the pre-determined page of data including the at least one booting instruction into a register associated with the non-volatile memory device;

receiving, by the internal controller, a command from a host processor coupled to the non-volatile memory device to read data stored in the register, wherein the command includes an address identifying a location within the register of the at least one booting instruction;

retrieving the at least one instruction from the register by the internal controller;

transmitting the at least one instruction from the internal controller to the host processor without storing the data in another memory.

9. The computer-accessible non-transitory storage medium of claim 8, wherein retrieving a pre-determined page of data is performed automatically by the system in response to detecting the reset signal.

10. The computer-accessible non-transitory storage medium of claim 8, wherein the instructions for causing the system to perform operations further comprises receiving a plurality of commands to read data stored in the register, wherein the data read in response to the plurality of commands comprises code for loading separate boot loader code to a random access memory associated with the processor.

11. The computer-accessible non-transitory storage medium of claim 10, wherein the separate boot loader code is adapted for loading operating system or application code from the nonvolatile memory to the random access memory.

12. The computer-accessible non-transitory storage medium of claim 8, wherein the nonvolatile memory is adapted to enable random access to any byte in the register in response to a command to read data stored in the register.

13. The computer-accessible non-transitory storage medium of claim 8, wherein the instructions for causing the system to perform operations further comprises converting an instruction fetch command from the processor into at least one command to read data stored in the register.

14. A data processing apparatus comprising:

a host having a host processor;

a non-volatile memory device that is separate from the host and that is configured to store data for the host, wherein the non-volatile device includes;

one or more non-volatile memory blocks;

a register; and

an internal controller configured to;

detect a reset signal; and

in response to detecting the reset signal;

retrieve a pre-determined page of data from a location in nonvolatile memory location, wherein each page of data is retrieved from the nonvolatile memory as a unit and the pre-determined page of data includes at least one instruction for booting the data processing apparatus;

load the pre-determined page of data including the at least one booting instruction into the register;

receive a command from the host processor to read data stored in the register, wherein the command includes an address identifying a location within the register of the at least one booting instruction;

retrieve the at least one instruction from the register; and

transmit the at least one instruction from the internal controller to the host processor without storing the data in another memory.

15. The apparatus of claim 14, wherein the non-volatile memory comprises a NAND flash memory.

16. The apparatus of claim 14, wherein retrieving a pre-determined page of data is performed automatically in response to detecting the reset signal.

17. The apparatus of claim 14, wherein the internal controller is further configured to receive a plurality of commands to read data stored in the register, wherein the data read in response to the plurality of commands comprises code for loading separate boot loader code to a random access memory associated with the processor.

18. The apparatus of claim 17, wherein the separate boot loader code is adapted for loading operating system or application code from the non-volatile memory to the random access memory.

19. The apparatus of claim 14, wherein the nonvolatile memory is adapted to enable random access to any byte in the register in response to a command to read data stored in the register.

20. The apparatus of claim 14, wherein the internal controller is further configured to convert an instruction fetch command from the processor into at least one command to read data stored in the register.