Enabling a non-core domain to control memory bandwidth in a processor

• US 8,832,478 B2
• Filed: 10/27/2011
• Issued: 09/09/2014
• Est. Priority Date: 10/27/2011
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Sodhi, Inder M., Rotem, Efraim, Rajwan, Doron, Wiessman, Eliezer, Wells, Ryan
• Primary Examiner(s): Phan, Raymond
• Application Number:
  US13/282,896
• Publication Number:
  US 20130111120A1
• Time in Patent Office: 1,048 Days
• Field of Search: 713300-340, 713500-501, 713/375
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Claims

1. A method comprising:

receiving a message from a non-core domain of a multi-domain processor, in a controller of the multi-domain processor, the message including a request to configure a mapping table to store a mapping between a frequency of the non-core domain and a minimum frequency of an interconnect that couples the non-core domain to a cache memory of the multi-domain processor;

writing a plurality of entries of the mapping table, each entry including a mapping between a non-core domain frequency and a minimum interconnect frequency; and

controlling a frequency of the interconnect using the mapping table, responsive to a frequency at which the non-core domain is operating.

2. The method of claim 1, wherein each of the plurality of entries includes a ratio between a non-core domain frequency and an interconnect frequency.

3. The method of claim 1, wherein each of the plurality of entries includes a non-core domain frequency and a corresponding interconnect minimum frequency.

4. The method of claim 1, further comprising accessing an entry of the mapping table using the frequency at which the non-core domain is operating.

5. The method of claim 1, further comprising obtaining the mapping table entries from a non-volatile storage associated with the non-core domain.

6. The method of claim 1, further comprising gathering statistics on memory boundedness of a workload executing on the non-core domain.

7. The method of claim 1, further comprising limiting the interconnect frequency to less than the minimum interconnect frequency for a corresponding frequency at which the non-core domain is operating when a core domain of the multi-domain processor is thermally or power limited.

8. A processor comprising:

a core domain including at least one core to execute instructions;

a non-core domain including at least one execution unit to execute instructions transparent to an operating system (OS), wherein a driver for the non-core domain is to control execution on the non-core domain;

a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor; and

a power controller to control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain.

9. The processor of claim 8, wherein the driver is to request the power controller to update the memory interconnect frequency based on the memory boundedness.

10. The processor of claim 8, wherein the driver is to determine the memory boundedness based on statistics collected during execution of the workload on the non-core domain.

11. The processor of claim 8, wherein the power controller includes a mapping table to map a frequency of the non-core domain to a minimum memory interconnect frequency.

12. The processor of claim 9, wherein the memory interconnect is part of the core domain, and the power controller is to update a frequency of the core domain responsive to the non-core domain driver request.

13. The processor of claim 9, wherein the power controller is to control the memory interconnect frequency to be a maximum of a frequency requested by the driver and a core domain frequency requested by the OS.

14. The processor of claim 11, wherein the driver is to communicate entries of the mapping table to the power controller via a mailbox interface.

15. The processor of claim 11, wherein the driver is to provide a first set of entries for the mapping table when the processor is enabled, and to update at least some of the first set of entries based on a change to a workload of the non-core domain.

16. The processor of claim 15, wherein the power controller is to reduce the memory interconnect frequency to the core domain frequency when the non-core domain enters a low power mode.

17. A system comprising:

a multi-domain processor including a core domain having at least one core and a memory interconnect, a non-core domain, and a system agent domain, the system agent domain including a mapping table to map a frequency of the non-core domain to a minimum frequency of the memory interconnect, wherein the non-core domain is to send a request to the system agent domain to cause an update to the memory interconnect frequency based at least in part on a workload being executed on the non-core domain; and

a dynamic random access memory (DRAM) coupled to the multi-domain processor.

18. The system of claim 17, wherein a driver of the non-core domain is to populate the mapping table via communication with a mailbox interface of the system agent domain.

19. The system of claim 18, wherein the driver is to write an indicator and an address into a first register of the mailbox interface and to write data into a second register of the mailbox interface, and responsive to the indicator the system agent domain is to write the data into an entry of the mapping table addressed by the address in the first register.

20. The system of claim 18, wherein the system agent domain is to control the memory interconnect frequency to be a maximum of a frequency requested by the driver and a core domain frequency requested by an operating system.

21. The system of claim 20, wherein the power controller is to reduce the memory interconnect frequency to the core domain frequency when the non-core domain enters a low power mode.