Systems and methods for generating dynamic super blocks

• US 8,832,507 B2
• Filed: 08/23/2010
• Issued: 09/09/2014
• Est. Priority Date: 08/23/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Post, Daniel J., Thio, Hsiao
• Primary Examiner(s): MASKULINSKI, MICHAEL C
• Application Number:
  US12/861,718
• Publication Number:
  US 20120047409A1
• Time in Patent Office: 1,478 Days
• Field of Search: 714/718
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes

Abstract

Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks from one or more dies of a NVM. The subset of memory locations may be selected based on at least one reliability measurement of the subset of memory locations. In some embodiments, in response to detecting one or more access failures in a portion of the dynamic super block, the NVM interface can retire at least a portion of the dynamic super block. In some embodiments, the NVM interface can reconstruct a new dynamic super block from the dynamic super block by progressively increasing the size of the new dynamic super block.

Claims

1. A method for generating dynamic super blocks for a non-volatile memory, the non-volatile memory comprising a plurality of physical blocks and each physical block comprising a plurality of physical pages, the method comprising:

determining that at least one physical page of one of the physical blocks is not suitable for storing data in an original mode, but is suitable for storing data in a mode that has a lower capacity than the original mode, wherein the at least one determined page is mapped to a first block that requires its physical pages to store data in the original mode;

remapping the at least one determined page from the first block to a dynamic super block, wherein the dynamic super block is a block that requires its physical pages to store data in the mode that has a lower capacity than the original mode, and wherein a number of physical pages mapped to the dynamic super block increases as additional determined pages are remapped to the dynamic super block; and

accessing the at least one physical page mapped to the dynamic super block in the mode that has a lower capacity than the original mode.

2. The method of claim 1, wherein the mode is a lower page only mode.

3. The method of claim 2, wherein the accessing the plurality of memory locations of the dynamic super block comprises accessing lower pages of each block of a plurality of blocks of the dynamic super block in a virtual single level cell (“

SLC”

) mode.

4. The method of claim 1, wherein the determining comprises detecting at least one access failure in a first subset of word lines of the physical block.

5. The method of claim 4, wherein the selecting comprises further comprising:

selecting a second subset of word lines of the physical block;

performing at least one test on the second subset of word lines;

determining that the second subset of word lines passes the at least one test; and

selecting the second subset of word lines as the subset of memory locations determined page.

6. The method of claim 1, wherein the determining comprises:

determining that a memory location of the block has a raw bit error rate that is below a pre-determined threshold;

performing at least one test on the memory location;

selecting the memory location as the at least on determined page if the memory location passes the at least one test.

7. The method of claim 1, wherein the accessing the plurality of memory locations of the dynamic super block comprises programming data into the plurality of memory locations in a SLC mode.

8. A memory interface for accessing a non-volatile memory, the non-volatile memory comprising a plurality of dies, each die comprising a plurality of physical blocks, the memory interface comprising:

a bus controller operative to communicate with the non-volatile memory; and

control circuitry operative to;

determine that a block of a die of the plurality of dies is not suitable for storing data in a multi-level cell (“

MLC”

) mode, wherein the determined block is mapped to a first block that requires its data to be stored in the MLC mode; and

remap the determined block from the first block to a dynamic single level cell (“

SLC”

) super block, wherein the dynamic SLC super block is a block that requires its data to be stored in a SLC mode that has a lower capacity than the MLC mode, and wherein a number of physical blocks mapped to the dynamic SLC super block increases as additional determined blocks are remapped to the dynamic SLC super block.

9. The memory interface of claim 8, wherein the control circuitry is operative to direct the bus controller to access memory locations of the dynamic SLC super block in a virtual SLC mode.

10. The memory interface of claim 9, wherein the data stored in the determined block is stored in lower pages of the block.

11. The memory interface of claim 8, wherein the control circuitry is operative to direct the bus controller to program data into memory locations of the dynamic SLC super block in a SLC mode.

12. The memory interface of claim 8, wherein the control circuitry is operative to:

detect at least one access failure in a portion of the dynamic SLC super block; and

retire at least a portion of the dynamic SLC super block.

13. The memory interface of claim 12, wherein the control circuitry is operative to retire the dynamic SLC super block.

14. The memory interface of claim 12, wherein the control circuitry is operative to retire only the portion of the dynamic SLC super block that has the at least one access failure.

15. A method for managing grown bad blocks of a non-volatile memory, the method comprising:

selecting at least a subset of memory locations of multiple grown bad blocks of the non-volatile memory to form a dynamic super block;

detecting that the dynamic super block needs to be erased;

preparing the dynamic super block for reprogramming; and

reconstructing a new dynamic super block from the dynamic super block by progressively increasing the size of the new dynamic super block.

16. The method of claim 15, wherein each grown bad block of the multiple grown bad blocks is on a different die of the non-volatile memory.

17. The method of claim 15, wherein the selecting further comprises programming only recoverable data in the dynamic super block.

18. The method of claim 17, wherein the recoverable data comprises at least one of user data, index page, swap page files, and translation layer metadata.

19. The method of claim 17, wherein the selecting further comprises aliasing the recoverable data at the end of the dynamic super block.

20. The method of claim 15, wherein the selecting further comprises applying error correction coding (“

ECC”

) engines that have higher strengths to data stored in the dynamic super block.

21. The method of claim 15, wherein the selecting further comprises using a higher number of parity pages in the dynamic super block.

22. The method of claim 15, wherein the reconstructing further comprises:

determining first memory locations of the dynamic super block with reliability measurements that exceed a first pre-determined threshold; and

selecting the first memory locations as the new dynamic super block.

23. The method of claim 22, further comprising:

determining that additional spare memory locations are needed;

determining second memory locations of the dynamic super block with reliability measurements that exceed a second pre-determined threshold, wherein the second pre-determined threshold is lower than the first pre-determined threshold; and

adding the second memory locations to the new dynamic super block.

24. The method of claim 15, wherein the reconstructing further comprises selecting memory locations based on physical positions of the memory locations in the non-volatile memory.

25. The method of claim 24, wherein the memory locations are selected based on a geometric relationship between the memory locations.