Techniques associated with a read and write window budget for a two level memory system

• US 8,832,530 B2
• Filed: 09/26/2012
• Issued: 09/09/2014
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Pangal, Kiran, Damie, Prashant
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US13/627,380
• Publication Number:
  US 20140089762A1
• Time in Patent Office: 713 Days
• Field of Search: 714/719, 714/773, 365/185.12, 365/185.24
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.

Claims

1. A method comprising:

establishing a read and write window budget for a two level memory (2LM) system including a first level memory and a second level memory, the read and write window budget including a combination of a first set of memory addresses and a second set of memory addresses of the second level memory, the first set of memory addresses associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses;

receiving a write request to write data to the 2LM system; and

causing the data to be written to the second level memory based on the read and write window budget.

2. The method of claim 1, comprising the non-volatile memory cells associated with the first set of memory addresses to store the data via use of a foreground write process that includes no error correction.

3. The method of claim 2, comprising the non-volatile memory cells associated with the second set of memory addresses to store at least a portion of the data via use of a background write process that includes:

implementing an error correction code (ECC) scheme for the at least portion of the data written to the non-volatile memory cells associated with the second set of memory address via use of the foreground write process;

causing the at least portion of the data to be stored in a write cache separate from the second level memory following implementation of the ECC scheme; and

causing the at least portion of the data to be written back to the non-volatile memory cells associated with the second set of memory addresses using a multiple pulse-verification algorithm capable of narrowing cell threshold voltage distributions for the memory cells associated with the second set of memory addresses compared to the cell threshold voltage distributions for the non-volatile memory cells associated with the first set of memory addresses.

4. The method of claim 3, comprising:

receiving a subsequent write request to write additional data; and

causing the additional data to be written to the second level memory based on the read and write window budget, the additional data to be written to non-volatile memory cells associated with a third set of memory addresses via use of the foreground write process and at least some of the additional data to be written to non-volatile memory cells associated with a fourth set of memory addresses via use of the background write process.

5. The method of claim 4, comprising the second set of memory addresses being different than the fourth set of memory addresses.

6. The method of claim 4, comprising the third set of memory addresses and the second set of memory addresses including at least one common memory address and writing the additional data to a non-volatile memory cell associated with the at least one common memory address includes:

determining a status of the background write process to the non-volatile memory cell for writing data associated with the previously received write request; and

causing the additional data to be written to the second level memory based on the status of the background write process.

7. The method of claim 6, comprising the status of the background write process indicating completion of the background write process and causing the additional data to be written to the second level memory includes writing the additional data to the non-volatile memory cell using the foreground write process.

8. The method of claim 6, comprising the status of the background write process indicating partial completion of the background write process and causing the additional data to be written to the second level memory to include:

causing the additional data to update data associated with the previously received write request that was written to the write cache as a result of the partially completed background write process;

scheduling the updated data to be written to the non-volatile memory cell in the second level memory; and

using the foreground write process or the background write process to cause the updated data to be written to the non-volatile memory cell in the second level memory.

9. The method of claim 3, comprising:

receiving a read request to read data from a memory address included in the second set of memory addresses;

determining a status of the background write process for writing the data associated with the received write request to a non-volatile memory cell associated with the memory address; and

causing the data to be read based on the status of the background write process.

10. The method of claim 9, comprising the status of the background write process indicating completion of the background write process and causing the data to be read includes causing the data to be read from the non-volatile memory cell associated with the memory address.

11. The method of claim 9, comprising the status of the background write process indicating partial completion of the background write process and causing the data to be read includes causing the data to be read from the write cache used to at least partially complete the background write process for data stored at the non-volatile memory cell associated with the memory address.

12. The method of claim 3, comprising establishing the read and write window budget based on meeting both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory, the foreground write process having a faster completion time compared to background write process, the background write process having lower errors compared to the foreground write process.

13. The method of claim 1, comprising the non-volatile memory cells to include one of phase change memory, phase change memory and switch, NAND flash memory, NOR flash memory or ferroelectric memory.

14. The method of claim 1, the first level memory of the 2LM system comprising volatile memory to include one of dynamic random access memory or static random access memory.

15. An apparatus at a wireless device comprising:

a processor circuit;

a budget component arranged for execution by the processor circuit to establish a read and write window budget for a two level memory (2LM) system including a first level memory and a second level memory, the read and write window budget including a combination of a first set of memory addresses and a second set of memory addresses of the second level memory, the first set of memory addresses associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses; and

a request component arranged for execution by the processor circuit to receive a write request to write data to the 2LM system, the request component also arranged to cause the data to be written to the second level memory based on the established read and write window budget.

16. The apparatus of claim 15, comprising:

a foreground component arranged for execution by the processor circuit to use a foreground write process to cause the data to be written to the non-volatile memory cells associated with the first set of memory addresses, the foreground write process to include no error correction; and

a background component arranged for execution by the processor circuit to use a background write process to cause at least a portion of the data to be written to the non-volatile memory cells associated with the second set of memory addresses, use of the background write process to include the background component being arranged to;

implement an error correction code (ECC) scheme for the at least portion of the data written to the non-volatile memory cells associated with the second set of memory addresses via use of the foreground write process;

cause the at least portion of the data to be stored to a write cache separate from the second level memory following implementation of the ECC scheme; and

cause the at least portion of the data to be written back to the non-volatile memory cells associated with the second set of memory addresses using a multiple pulse-verification algorithm capable of narrowing cell threshold voltage distributions for the memory cells associated with the second set of memory addresses compared to the cell threshold voltage distributions for the non-volatile memory cells associated with the first set of memory addresses.

17. The apparatus of claim 16, comprising:

the request component arranged to receive a subsequent write request to write additional data and cause the additional data to be written to the second level memory based on the read and write window budget, the additional data to be written to non-volatile memory cells associated with a third set of memory addresses and at least a portion of the additional data to be written to non-volatile memory cells associated with a fourth set of memory addresses;

the foreground component arranged to use the foreground write process to cause the additional data to be written to the non-volatile memory cells associated with the third set of memory addresses; and

the background component arranged to use the background write process to cause the at least portion of the additional data to be written to the non-volatile memory cells associated with the fourth set of memory addresses.

18. The apparatus of claim 16, comprising the third set of memory addresses and the second set of memory addresses including at least one common memory address associated with a non-volatile memory cell, the request component arranged to cause the additional data to be written to the non-volatile memory cell to include the request component also arranged to:

determine a status of the background write process used by the background component to cause the data associated with the previously received write request to be written to the non-volatile memory cell; and

cause the additional data to be written to the non-volatile memory cell based on the status of the background write process.

19. The apparatus of claim 18, comprising the status of the background write process indicating that the background component has completed the background write process for writing the data associated with the previously received write request to the at least one common memory address associated with the non-volatile memory cell, the request component also arranged to have the additional data caused to be written to the non-volatile memory cell by the foreground component, the foreground component to cause the additional data to be written to the non-volatile memory cell using the foreground write process.

20. The apparatus of claim 18, comprising the status of the background write process indicating that the background component has partially completed the background write process for writing the data associated with the previously received write request to the at least one common memory address associated with the non-volatile memory cell, the request component also arranged to have the additional data written to the second level memory by:

causing the additional data to update data associated with the previously received write request that was caused to be written to the write cache by the background component as a result of the background component partially completing the background write process;

scheduling the additional data to be written to the non-volatile memory cell in the second level memory; and

causing the foreground component to cause the additional data from the write cache to be written to the non-volatile memory cell in the second level memory using the foreground write process or cause the background component to cause the additional data from the write cache to be written to the non-volatile memory cell in the second level memory using the background write process.

21. The apparatus of claim 16, comprising the budget component arranged to establish the read and write window budget based on meeting both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory, the foreground write process to have a faster completion time compared to background write process, the background write process to have lower errors compared to the foreground write process.

22. At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed on a system cause the system to:

establish a read and write window budget for a two level memory (2LM) system including a first level memory and a second level memory, the read and write window budget including a combination of a first set of memory addresses and a second set of memory addresses of the second level memory, the first set of memory addresses associated with non-volatile memory cells configured to have wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses;

receive a write request to write data to the 2LM system; and

cause the data to be written to the second level memory based on the read and write window budget.

23. At least one non-transitory machine readable medium of claim 22, the plurality of instructions to also cause the system to:

cause the data to be written to the non-volatile memory cells associated with the first set of memory addresses via use of a foreground write process that includes no error correction; and

cause at least a portion of the data to be written to the non-volatile memory cells associated with the second set of memory addresses via use of a background write process, the background write process to cause the system to;

implement an error correction code (ECC) scheme for the at least portion of the data written to the non-volatile memory cells associated with the second set of memory address via use of the foreground write process;

store the at least portion of the data in a write cache separate from the second level memory following implementation of the ECC scheme; and

write back the at least portion of the data to the non-volatile memory cells associated with the second set of memory addresses using a multiple pulse-verification algorithm capable of narrowing cell threshold voltage distributions for the memory cells associated with the second set of memory addresses compared to the cell threshold voltage distributions for the non-volatile memory cells associated with the first set of memory addresses.

24. At least one non-transitory machine readable medium of claim 23, comprising the system to establish the read and write window budget based on meeting both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory, the foreground write process having a faster completion time compared to background write process, the background write process having lower errors compared to the foreground write process.