×

Distributing spare latch circuits in integrated circuit designs

  • US 8,832,626 B2
  • Filed: 03/12/2013
  • Issued: 09/09/2014
  • Est. Priority Date: 12/09/2011
  • Status: Active Grant
First Claim
Patent Images

1. A method implemented by a computer, comprising:

  • determining, using the computer, placements of logic blocks and local clock buffers in an integrated circuit (IC) design;

    determining, using the computer, an allocation of spare latch circuits to the logic blocks in the IC design based on corresponding design input factors;

    determining, using the computer, a correspondence between the local clock buffers and logic blocks in the IC design; and

    based on the determined correspondence between the local clock buffers and the logic blocks, placing, the number of the spare latch circuits in the IC design in accordance with the determined allocation of the spare latch circuits, wherein the placing distributes the number of the spare latch circuits among the local clock buffers.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×