Distributing spare latch circuits in integrated circuit designs

• US 8,832,626 B2
• Filed: 03/12/2013
• Issued: 09/09/2014
• Est. Priority Date: 12/09/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Agrawal, Mitesh A., Balasubramanian, Santosh, Chatnahalli, Pradeep N., Shivaram, Prasad
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/796,259
• Publication Number:
  US 20130191801A1
• Time in Patent Office: 546 Days
• Field of Search: 716111-114, 716/119
• US Class Current: 716/114
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.

Claims

1. A method implemented by a computer, comprising:

determining, using the computer, placements of logic blocks and local clock buffers in an integrated circuit (IC) design;

determining, using the computer, an allocation of spare latch circuits to the logic blocks in the IC design based on corresponding design input factors;

determining, using the computer, a correspondence between the local clock buffers and logic blocks in the IC design; and

based on the determined correspondence between the local clock buffers and the logic blocks, placing, the number of the spare latch circuits in the IC design in accordance with the determined allocation of the spare latch circuits, wherein the placing distributes the number of the spare latch circuits among the local clock buffers.

2. The method of claim 1, wherein the distributing the number of spare latch circuits among the local clock buffers includes dividing the spare latch circuits equally among respective local clock buffers of the logic blocks.

3. The method of claim 1, wherein the design input factors are based on spare latch design factors, including at least one:

a design age factor, a design bug factor, a design complexity factor, and a verification coverage factor.

4. The method of claim 3, further comprising obtaining one or more of the spare latch design factors from a hardware definition language (HDL) information corresponding to the logic blocks.

5. The method of claim 3, further comprising receiving one or more of the spare latch design factors from a user via an interactive user interface.

6. The method of claim 3, further comprising retrieving one or more of the spare latch design factors from a logic block verification database.

7. The method of claim 1, wherein the determining the allocation of spare latch circuits comprises, for each of the logic blocks, determining a likelihood a logic block design will change based on the spare latch design factors of the logic block.

8. The method of claim 7, wherein the determining the likelihood the logic block design will change comprises:

determining a weighted average of the spare latch design factors for each of the logic blocks; and

normalizing each of the weighted averages across the plurality of the logic blocks.

9. The method of claim 1, wherein the spare latch circuits include a latch, a buffer and a clocking structure.

10. A computer program product comprising a computer usable storage device having a computer readable program stored in the computer usable storage device, wherein the computer readable program, when executed on a computing device, is operable to cause the computing device to:

determine logic blocks in an integrated circuit (IC) design, the logic blocks having respective attributes;

determine respective spare latch design factors of the logic blocks based on a combination of the respective attributes of the logic blocks;

determine, based on the respective spare latch design factors of the logic blocks, a relative probability of design change for each of the logic blocks; and

determine, based on the relative probability of design change for each of the logic blocks, a number of spare latch circuits to allocate among the logic blocks, wherein a logic block having a greater probability of design change is allocated a greater proportion of a total number of available spare latch circuits relative to a logic block having a lower probability of design change.

11. The computer program product of claim 10, wherein:

the number of spare latch circuits include at least one of a latch, a buffer and a clocking structure; and

the spare latch design factors include at least one of a design age factor, a design bug factor, a design complexity factor, and a verification coverage factor.

12. A computer program product comprising a computer usable storage device having a computer readable program stored in the computer usable storage device, wherein the computer readable program, when executed on a computing device, is operable to cause the computing device to:

determine logic blocks in an integrated circuit (IC) design;

determine, based on respective spare latch design factors of the logic blocks, a relative probability of design change for each of the logic blocks; and

determine, based on the relative probability of design change for each of the logic blocks, a number of spare latch circuits to allocate among the logic blocks, wherein a logic block having a greater probability of design change is allocated a greater proportion of a total number of available spare latch circuits relative to a logic block having a lower probability of design change,

wherein the computer readable program is operable to determine the relative probability of design change by;

determining a weighted average of the attributes for each of the logic blocks; and

normalizing each of the weighted averages across the logic blocks.