Method for optimising cell variant selection within a design process for an integrated circuit device

• US 8,832,629 B2
• Filed: 07/23/2010
• Issued: 09/09/2014
• Est. Priority Date: 07/23/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rozen, Anton, Priel, Michael, Seidenwar, Yaakov
• Primary Examiner(s): Whitmore, Stacy
• Assistant Examiner(s): Dimyan, Magid
• Application Number:
  US13/811,400
• Publication Number:
  US 20130125077A1
• Time in Patent Office: 1,509 Days
• Field of Search: 716/119, 716/126
• US Class Current: 716/119
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimization comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimization, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.

Claims

1. A method of generating a design for an integrated circuit device, the method comprising:

performing, using a computer, cell placement and signal routing for the integrated circuit device being designed using default cell layout information for cell variants of at least one cell type; and

performing cell variant optimization, wherein cell variant optimization comprises;

identifying at least one cell of the at least one cell type to be substituted,

substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell, and

during said performing cell variant optimisation, configuring a pin interconnect layout modification for mapping physical layout of at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.

2. The method of claim 1 wherein the method further comprises:

defining within at least one cell definition library a pin interconnect layout modification relative to the default cell layout for at least one variant of the at least one cell type; and

during said performing cell variant optimisation, configuring the pin interconnect layout modification for the alternative variant of the at least one identified cell as defined within the at least one cell definition library.

3. The method of claim 2 wherein the method comprises defining, within at least one cell definition library, cell layout information for the default cell variant and at least one alternative cell variant of the at least one cell type, the cell layout information comprising pin interconnect layout modification information for the at least one alternative cell variant.

4. The method of claim 2 wherein the method comprises defining, within at least one cell definition library, cell layout information for the default cell variant, and further defining, within the at least one cell definition library, a pin interconnect layout modification relative to the default cell layout for each alternative cell variant.

5. The method of claim 1 wherein the method comprises defining, within the at least one cell definition library, cell timing information for the default variant of the at least one cell type and a timing delta value for the at least one alternative variant of the at least one cell type.

6. The method of claim 1 wherein configuring a pin interconnect layout modification comprises configuring at least one connecting strip within a metal layer of the integrated circuit device between at least one pin contact of an alternative cell variant and at least one corresponding pin location within the respective default cell layout.

7. The method of claim 6 wherein configuring a pin interconnect layout modification comprises configuring at least one connecting strip within a metal layer of the integrated circuit device adjacent a polysilicon structure of the cell.

8. The method of claim 1, further including manufacturing the integrated circuit in accordance with the design.

9. An integrated circuit device created by way of a process comprising the method for optimising cell variant selection of claim 1.

10. A non-transitory computer-readable storage medium having executable program code stored therein for optimising cell variant selection within a design process for an integrated circuit device, the program code operable for:

performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type; and

performing cell variant optimization, wherein cell variant optimization comprises identifying at least one cell of the at least one cell type to be substituted,

substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell, and

during said performing cell variant optimisation, configuring a pin interconnect layout modification for mapping physical layout of at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.

11. The computer readable storage medium of claim 10, wherein the program code is further operable for:

defining within at least one cell definition library a pin interconnect layout modification relative to the default cell layout for at least one variant of the at least one cell type; and

during said performing cell variant optimisation, configuring the pin interconnect layout modification for the alternative variant of the at least one identified cell as defined within the at least one cell definition library.

12. The computer readable storage medium of claim 11 wherein the program code is further operable for defining, within at least one cell definition library, cell layout information for the default cell variant and at least one alternative cell variant of the at least one cell type, the cell layout information comprising pin interconnect layout modification information for the at least one alternative cell variant.

13. The computer readable storage medium of claim 11 wherein the program code is further operable for defining, within at least one cell definition library, cell layout information for the default cell variant, and further defining, within the at least one cell definition library, a pin interconnect layout modification relative to the default cell layout for each alternative cell variant.

14. The computer readable storage medium of claim 10 wherein the program code is further operable for defining, within the at least one cell definition library, cell timing information for the default variant of the at least one cell type and a timing delta value for the at least one alternative variant of the at least one cell type.

15. The computer readable storage medium of claim 10 wherein the program code operable to configure a pin interconnect layout modification comprises further program code operable for configuring at least one connecting strip within a metal layer of the integrated circuit device between at least one pin contact of an alternative cell variant and at least one corresponding pin location within the respective default cell layout.

16. The computer readable storage medium of claim 15 wherein the program code operable to configure a pin interconnect layout modification comprises further program code operable for configuring at least one connecting strip within a metal layer of the integrated circuit device adjacent a polysilicon structure of the cell.