Fuse for three dimensional solid-state battery

• US 8,835,029 B2
• Filed: 10/04/2011
• Issued: 09/16/2014
• Est. Priority Date: 10/04/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ellis-Monaghan, John J., Gambino, Jeffrey P., Peterson, Kirk D., Rankin, Jed H.
• Primary Examiner(s): Ryan, Patrick
• Assistant Examiner(s): MCCONNELL, WYATT P
• Application Number:
  US13/252,366
• Publication Number:
  US 20130084476A1
• Time in Patent Office: 1,078 Days
• Field of Search: None
• US Class Current: 429/61
• CPC Class Codes: H01M 10/02 Details of electrodes H01M4/00; of non-active parts H01M50/00
• CPC Class Codes: H01M 10/052 Li-accumulators
• CPC Class Codes: H01M 10/0562 Solid materials
• CPC Class Codes: H01M 10/058 Construction or manufacture
• CPC Class Codes: H01M 10/42 Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells H01M10/60 takes precedence
• CPC Class Codes: H01M 4/767 Multitubular sheaths or covers
• CPC Class Codes: H01M 50/503 characterised by the shape of the interconnectors
• CPC Class Codes: H01M 50/522 Inorganic material
• CPC Class Codes: H01M 50/529 Intercell connections through partitions, e.g. in a battery casing
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49108 Electric battery cell making

Abstract

A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.

Claims

1. A battery structure comprising:

a substrate;

a plurality of battery cells formed in the substrate;

a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells; and

a patterned fuse layer formed above the cathode electrode layer comprising a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays, wherein at least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array.

2. The battery structure of claim 1, wherein each of the battery cells comprises a barrier layer, an anode electrode layer, and an electrolyte layer separating the anode electrode layer and the patterned cathode electrode layer.

3. The battery structure of claim 2, wherein the plurality of sub-arrays are arranged in an array having rows and columns.

4. The battery structure of claim 3, wherein the patterned cathode electrode layer, the electrolyte layer and the barrier layer are arranged in a substantially stair step pattern along each side of the array.

5. A battery structure comprising:

a substrate;

a plurality of battery cells formed in the substrate;

a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells; and

a first patterned fuse layer formed above the cathode electrode layer comprising a first plurality of fuse wires structured to interconnect the sub-arrays, wherein at least one of the first plurality of fuse wires is structured to be blown to disconnect a single defective sub-array.

6. The battery structure of claim 5, wherein the plurality of sub-arrays are arranged in an array having rows and columns.

7. The battery structure of claim 6, further comprising a second patterned fuse layer formed above the cathode electrode layer comprising a second plurality of fuse wires, wherein the first plurality of fuse wires extends along each row of the array and the second plurality of fuse wires is arranged so as to electrically connect each of the sub-arrays to the first plurality of fuse wires.

8. The battery structure of claim 7, wherein the first plurality of fuse wires are formed between the rows of the array and wherein the second plurality of fuse wires are formed between the columns of the array.

9. A method of forming a battery structure comprising:

forming a plurality of battery cells in a substrate;

forming a cathode electrode layer overlying the plurality of battery cells;

patterning the cathode electrode layer to define a plurality of sub-arrays of the battery cells;

forming a fuse layer above the cathode electrode layer; and

patterning the fuse layer to form a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays, wherein at least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array.

10. The method of claim 9, wherein forming the plurality of battery cells comprises:

forming a plurality of trenches having sidewalls and a bottom in the substrate;

forming a barrier layer on the sidewalls and the bottom of the plurality of trenches and upon a surface of the substrate between the plurality of trenches;

forming an anode electrode layer overlying the barrier layer;

forming an electrolyte layer overlying the anode layer; and

forming the patterned cathode electrode layer overlying the electrolyte layer.

11. The method of claim 10, wherein patterning the cathode electrode layer further comprises arranging the plurality of sub-arrays in an array having rows and columns.

12. The method of claim 11, further comprising forming a first horizontal offset between the patterned cathode electrode layer and the electrolyte layer and forming a second horizontal offset between the electrolyte layer and the barrier layer along each side of the array.

13. A method of forming a battery structure comprising:

forming a plurality of battery cells in a substrate;

forming a cathode electrode layer overlying the plurality of battery cells;

patterning the cathode electrode layer to define a plurality of sub-arrays of the battery cells;

forming a fuse layer above the cathode electrode layer; and

patterning the fuse layer to form a plurality of fuse wires structured to interconnect the sub-arrays, wherein at least one of the plurality of fuse wires is structured to be blown to disconnect a single defective sub-array.

14. The method of claim 13, wherein patterning the cathode electrode layer further comprises arranging the plurality of sub-arrays in an array having rows and columns.

15. The method of claim 14, wherein patterning the plurality of fuse wires further comprises patterning a first plurality of fuse wires arranged substantially parallel to each other along each row of the array and patterning a second plurality of fuse wires arranged so as to electrically connect each of the sub-arrays to the first plurality of fuse wires.

16. The method of claim 15, further comprising forming a plurality of substantially vertically aligned electrically conductive vias to connect each of the second plurality of fuse wires to a corresponding sub-array.

17. The method of claim 15, wherein the first plurality of fuse wires are patterned between the plurality of rows of the array and wherein the second plurality of fuse wires are patterned between the plurality of columns of the array.

18. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a substrate;

a plurality of battery cells formed in the substrate;

a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells; and

a patterned fuse layer formed above the cathode electrode layer comprising a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays, wherein at least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array.