Integrated chip package structure using ceramic substrate and method of manufacturing the same

• US 8,835,221 B2
• Filed: 05/03/2013
• Issued: 09/16/2014
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lin, Mou-Shiung, Huang, Ching-Cheng, Lee, Jin-Yaun
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US13/887,093
• Publication Number:
  US 20130309812A1
• Time in Patent Office: 501 Days
• Field of Search: 438/107, 438/108, 438110-113, 438/118, 438/125, 438/458, 438/459, 257/777, 257/778
• US Class Current: 438/107
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Claims

1. A chip packaging method comprising:

joining a die and a substrate;

thinning said die;

after joining said die and said substrate, forming an opening in said substrate and exposing said die; and

forming a metal layer on said substrate and forming a via in said opening, said metal layer coupled to said die through said via in said substrate.

2. The method of claim 1, further comprising forming an insulation layer around said die.

3. The method of claim 2, wherein said insulation layer comprises polymer.

4. The method of claim 2, wherein said insulation layer comprises oxide.

5. The method of claim 2, wherein said insulation layer comprises epoxy.

6. The method of claim 1, wherein said substrate comprises organic material.

7. The method of claim 1, further comprising thinning said substrate.

8. The method of claim 7, wherein said thinning said substrate comprises grinding said substrate.

9. The method of claim 7, wherein said thinning said substrate is performed until said substrate has a thickness between 2 μ

m and 200 μ

m.

10. The method of claim 7, wherein said thinning said die is followed by said thinning said substrate.

11. The method of claim 1, wherein said thinning said die comprises grinding said die.

12. The method of claim 1, wherein said substrate comprises ceramic material.

13. The method of claim 1, wherein said metal layer is formed using a process comprising sputtering.

14. The method of claim 1, wherein said metal layer is formed using a process comprising electroplating.

15. The method of claim 1, after forming said metal layer on said substrate, further comprising forming a bump on said metal layer, wherein said bump comprises gold.

16. The method of claim 1, after forming said metal layer on said substrate, further comprising forming a solder bump on said metal layer.

17. The method of claim 1, after forming said metal layer on said substrate, further comprising performing a singularizing process to form multiple chip package structures.

18. The method of claim 17, wherein one of said chip package structures comprises only one of said die.

19. The method of claim 17, wherein one of said chip package structures comprises a plurality of said die.

20. The method of claim 1, wherein said metal layer is formed using a process comprising electroless plating.

21. The method of claim 1, wherein said opening is formed using a process comprising drilling.

22. The method of claim 1, wherein said opening is formed using a process comprising etching.

23. The method of claim 1, wherein said substrate comprises glass material.

24. The method of claim 1, after forming said metal layer on said substrate, further comprising forming an insulation layer on said metal layer.

25. The method of claim 24, wherein said insulation layer comprises polyimide, benzocyclobutene, porous dielectric material, or stress buffer material.

26. The method of claim 1, after forming said metal layer on said substrate, further comprising forming an insulation layer on said metal layer and forming a first metal layer on said insulation layer, said first metal layer coupled to said metal layer through a via in said insulation layer.

27. The method of claim 26, wherein said insulation layer comprises polyimide, benzocyclobutene, porous dielectric material, or stress buffer material.

28. The method of claim 1, further comprising forming a passive device on said substrate.

29. The method of claim 28, wherein said passive device comprises a capacitor, a resistor, an inductor, a filter, a wave guide, or a micro electronic mechanical sensor (MEMS).

30. The method of claim 1, after thinning said die, further comprising joining said die and a carrier.

31. The method of claim 30, wherein said carrier comprises ceramic material.

32. The method of claim 1, wherein said joining said die and said substrate comprises joining a plurality of said die and said substrate, said metal layer comprising an interconnect coupled to multiple of said plurality of said die.

33. The method of claim 1, wherein said metal layer comprises a power bus or a ground bus.

34. The method of claim 1, wherein said die comprises a thin-film circuit layer formed therein, said metal layer having a thickness greater than that of said thin-film circuit layer.

35. The method of claim 1, wherein said metal layer comprises an interconnect connecting multiple portions of said die.

36. The method of claim 1, wherein said metal layer comprises copper.