Semiconductor process

• US 8,835,243 B2
• Filed: 05/04/2012
• Issued: 09/16/2014
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lu, Shui-Yen, Tsai, Tzung-I
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US13/463,819
• Publication Number:
  US 20130295735A1
• Time in Patent Office: 865 Days
• Field of Search: 438/230, 438/704, 438/233, 257/69, 257/E21.64, 216/57
• US Class Current: 438/230
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A semiconductor process includes the following steps. A first structure and a second structure are formed on a substrate. An oxide layer is entirely formed to cover the first structure and the second structure. A nitride layer is formed to entirely cover the oxide layer. A dry etching process is performed to remove a part of the nitride layer on the first structure. A wet etching process is performed to entirely remove the nitride layer and the oxide layer on the first structure and the second structure.

Claims

1. A semiconductor process, comprising:

forming a first structure and a second structure on a substrate;

forming an oxide layer to entirely cover the first structure and the second structure;

forming a nitride layer to entirely cover the oxide layer;

performing a dry etching process to remove only a part of the nitride layer directly above the first structure, wherein the part of the nitride layer located on the sides of the first structure above the substrate and all of the oxide layer remain intact; and

performing a wet etching process to entirely remove the nitride layer and the oxide layer on the first structure and the second structure.

2. The semiconductor process according to claim 1, further comprising:

performing an annealing process to enable the nitride layer on the second structure to induce stress to the substrate beneath the second structure after the dry etching process is performed.

3. The semiconductor process according to claim 1, further comprising:

performing a source/drain ion implantation process to form a source/drain region in the substrate beside each of the first structure and the second structure after the wet etching process is performed; and

performing an annealing process to activate the source/drain region.

4. The semiconductor process according to claim 1, wherein the nitride layer right above the top surface of the first structure is entirely removed while the nitride layer right above the sidewalls of the first structure is partially removed, as the dry etching process is performed.

5. The semiconductor process according to claim 1, wherein the first structure is used for forming a PMOS transistor and the second structure is used for forming an NMOS transistor.

6. The semiconductor process according to claim 1, wherein the nitride layer comprises a stress layer.

7. The semiconductor process according to claim 1, wherein each of the first structure and the second structure comprises a gate structure on the substrate and a spacer on the substrate beside the gate structure.

8. The semiconductor process according to claim 7, wherein the spacer is formed by a precursor of hexachlorodisilane (HCD).

9. The semiconductor process according to claim 1, wherein the etchant of the wet etching process comprises phosphoric acid (H3PO4).

10. The semiconductor process according to claim 9, wherein the etchant of the wet etching process comprises dilute hydrofluoric acid (DHF).

11. The semiconductor process according to claim 1, further comprising:

performing a source/drain ion implantation process to form a source/drain region in the substrate beside each of the first structure and the second structure before the oxide layer is formed.

12. The semiconductor process according to claim 11, further comprising:

performing an annealing process to activate the source/drain region after the source/drain ion implantation process is performed.

13. The semiconductor process according to claim 11, further comprising:

performing an annealing process to activate the source/drain region and to enable the nitride layer on the second structure to induce stress to the substrate beneath the second structure after the dry etching process is performed.

14. A semiconductor process, comprising:

forming a structure on a substrate;

forming an oxide layer entirely covering the structure;

forming a nitride layer entirely covering the oxide layer;

performing a dry etching process to remove only a part of the nitride layer directly above the structure, wherein the part of the nitride layer located on the sides of the structure above the substrate and all of the oxide layer remain intact; and

performing a wet etching process to entirely remove the nitride layer and the oxide layer on the structure.

15. The semiconductor process according to claim 14, wherein the structure comprises a gate structure on the substrate and a spacer on the substrate beside the gate structure.

16. The semiconductor process according to claim 15, wherein the spacer is formed by a precursor of hexachlorodisilane (HCD).

17. The semiconductor process according to claim 14, wherein the etchant of the wet etching process comprises phosphoric acid (H3PO4).

18. The semiconductor process according to claim 17, wherein the etchant of the wet etching process comprises dilute hydrofluoric acid (DHF).

19. The semiconductor process according to claim 14, further comprising:

performing a source/drain ion implantation process to form a source/drain region in the substrate beside the structure before the oxide layer is formed.

20. The semiconductor process according to claim 19, further comprising:

performing an annealing process to activate the source/drain region after the source/drain ion implantation process is performed.