Retrograde substrate for deep trench capacitors

• US 8,835,249 B2
• Filed: 07/08/2013
• Issued: 09/16/2014
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Haensch, Wilfried E., Leobandung, Effendi, Yamashita, Tenko, Yeh, Chun-Chen
• Primary Examiner(s): Geyer, Scott B
• Assistant Examiner(s): Seven, Evren
• Application Number:
  US13/936,752
• Publication Number:
  US 20130309835A1
• Time in Patent Office: 435 Days
• Field of Search: None
• US Class Current: 438/245
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H01L 31/112 characterised by field-effect operation, e.g. junction field-effect phototransistor
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A method for forming a semiconductor device includes forming a deep trench in a substrate having a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth. A region around the deep trench is doped to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion. A deep trench capacitor is formed in the deep trench using the buried plate as one electrode of the capacitor. An access transistor is formed to charge or discharge the deep trench capacitor. A well is formed in the first doped portion.

Claims

1. A method for forming a semiconductor device, comprising:

forming a deep trench in a substrate having a buried insulator layer, a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth;

doping a region around the deep trench to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion;

forming a deep trench capacitor in the deep trench using the buried plate as one electrode of the capacitor;

forming an access transistor to charge or discharge the deep trench capacitor;

forming a well in the first doped portion under the buried insulator layer that does not contact the deep trench capacitor; and

forming at least one device in the well.

2. The method as recited in claim 1, wherein the first doped portion includes a p−

doping and the second doped portion includes an n+ type doping and the step of doping a region around the deep trench to form a buried plate includes doping the region with an n+ doping.

3. The method as recited in claim 1, wherein the substrate includes a semiconductor-on-insulator substrate having semiconductor material formed on a buried dielectric layer over a bulk substrate, and the step of forming an access transistor includes forming the access transistor in the semiconductor material.

4. The method as recited in claim 1, wherein the access transistor includes a fin field effect transistor.

5. The method as recited in claim 1, further comprising forming a contact, which extends through the first doped portion into the second doped portion to provide an electrical path between the buried plate and a ground.

6. The method as recited in claim 1, wherein forming the well includes forming the well by implanting dopants that extend from an upper surface of the first doped portion to a position above the first depth.

7. The method as recited in claim 1, wherein the well includes an n−

doping type when the first doped portion includes a p−

doping type.

8. The method as recited in claim 1, wherein the well includes a p+ doping type when the first doped portion includes a p−

doping type.

9. The method as recited in claim 1, further comprising forming a diode in the well.

10. The method as recited in claim 1, further comprising forming an NPN junction in the well.

11. A method for forming a semiconductor device, comprising:

providing a substrate having a buried insulator layer, a first doped portion to a first depth and a second doped portion below the first depth;

forming a deep trench in the substrate, the deep trench extending below the first depth;

doping a region around the deep trench to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion;

forming a deep trench capacitor in the deep trench using the buried plate as one electrode of the capacitor;

forming an access transistor to charge or discharge the deep trench capacitor;

forming a well in the first doped portion under the buried insulator layer that does not contact the deep trench capacitor, the well having a different dopant type than the first doped portion; and

forming at least one device in the well.

12. The method as recited in claim 11, wherein the first doped portion includes a p−

doping and the second doped portion includes an n+ doping and the step of doping a region around the deep trench to form a buried plate includes doping the region with an n+ doping.

13. The method as recited in claim 11, wherein the substrate includes a semiconductor-on-insulator substrate having semiconductor material formed on a buried dielectric layer over a bulk substrate, and the step of forming an access transistor includes forming the access transistor in the semiconductor material.

14. The method as recited in claim 11, wherein the access transistor includes a fin field effect transistor.

15. The method as recited in claim 11, further comprising forming a contact, which extends through the first doped portion into the second doped portion to provide an electrical path between the buried plate and a ground.

16. The method as recited in claim 11, wherein forming the well includes forming the well by implanting dopants that extend from an upper surface of the first doped portion to a position above the first depth.

17. The method as recited in claim 11, wherein the well includes an n−

doping when the first doped portion includes a p−

doping.

18. The method as recited in claim 11, wherein the well includes a p+ doping when the first doped portion includes a p−

doping type.

19. The method as recited in claim 11, further comprising forming an electrostatic discharge device in the well.