Control of threshold voltages in high-k metal gate stack and structures for CMOS devices

• US 8,835,260 B2
• Filed: 07/12/2012
• Issued: 09/16/2014
• Est. Priority Date: 11/16/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Jagannathan, Hemanth, Ando, Takashi, Narayanan, Vijay
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/547,792
• Publication Number:
  US 20120276720A1
• Time in Patent Office: 796 Days
• Field of Search: 438/197, 438/199, 438/216, 438/275, 438/287, 438/591, 257/204, 257/206, 257/E21.242, 257/E21.255
• US Class Current: 438/275
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation

Abstract

A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

Claims

1. A method of forming a semiconductor structure on a semiconductor substrate, the semiconductor structure having a first semiconductor device including a first patterned material stack and a second semiconductor device including a second patterned material stack, the method comprising:

forming a germanium (Ge) material layer on the semiconductor substrate;

forming a diffusion barrier layer on the Ge material layer only in the first patterned material stack;

forming a high-k dielectric having a dielectric constant greater than approximately 3.9;

forming a metal oxide or nitride layer in the first patterned material stack interfacing with the high-k dielectric; and

forming a conductive electrode layer above the high-k dielectric.

2. The method of claim 1, wherein the Ge material layer in the second patterned material stack interfaces directly with the high-k dielectric.

3. The method of claim 1, wherein the metal oxide or nitride layer in the first patterned material stack interfaces directly with the high-k dielectric.

4. The method of claim 1, wherein forming a diffusion barrier layer only in the first patterned material stack comprises:

forming the diffusion barrier layer on the Ge material layer on the first patterned material stack and the second patterned material stack;

forming a photo resist layer on the diffusion barrier layer of the first patterned material stack; and

removing the diffusion barrier layer from the second patterned material stack.

5. The method of claim 1, wherein forming a diffusion barrier layer only in the first patterned material stack comprises:

forming a masking layer on the second patterned material stack; and

forming the diffusion barrier layer on the Ge material layer on the first patterned material stack.