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Control of threshold voltages in high-k metal gate stack and structures for CMOS devices

  • US 8,835,260 B2
  • Filed: 07/12/2012
  • Issued: 09/16/2014
  • Est. Priority Date: 11/16/2009
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor structure on a semiconductor substrate, the semiconductor structure having a first semiconductor device including a first patterned material stack and a second semiconductor device including a second patterned material stack, the method comprising:

  • forming a germanium (Ge) material layer on the semiconductor substrate;

    forming a diffusion barrier layer on the Ge material layer only in the first patterned material stack;

    forming a high-k dielectric having a dielectric constant greater than approximately 3.9;

    forming a metal oxide or nitride layer in the first patterned material stack interfacing with the high-k dielectric; and

    forming a conductive electrode layer above the high-k dielectric.

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