Method for improving thermal stability of metal gate

• US 8,835,294 B2
• Filed: 03/16/2010
• Issued: 09/16/2014
• Est. Priority Date: 03/16/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chew, Han-Guan, Zhu, Ming, Teo, Lee-Wee, Chuang, Harry Hak-Lay, Chen, Yi-Ren
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US12/724,984
• Publication Number:
  US 20110230042A1
• Time in Patent Office: 1,645 Days
• Field of Search: None
• US Class Current: 438/591
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/3215 Doping the layers
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

Claims

1. A method of fabricating a semiconductor device comprising:

providing a semiconductor substrate;

forming a gate structure on the substrate, the gate structure including a dummy gate, an interfacial layer, and a dielectric layer;

removing the dummy gate from the gate structure thereby forming a trench, such that the dielectric layer remains within the trench;

forming a work function metal layer partially filling the trench, the work function metal layer formed over the dielectric layer;

forming a fill metal layer filling a remainder of the trench;

performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench; and

implanting one of Si, C, and Ge into a remaining portion of the fill metal layer.

2. The method of claim 1, wherein implanting one of Si, C, and Ge includes utilizing an energy ranging from about 2 keV to about 7 keV and a dosage ranging from about 1E15 atoms/cm² to about 1E16 atoms/cm².

3. The method of claim 1, further comprising performing an annealing after the implantation, the annealing being performed at a temperature ranging from about 200°

C. to about 400°

C.

4. The method of claim 1, wherein implanting one of Si, C, and Ge includes implanting one of Si, C, and Ge such that the one of Si, C, and Ge in the fill metal layer, measured in atoms/cm³, has a percentage ranging from about 1E-5 to about 1E-8.

5. The method of claim 1, wherein forming the fill metal layer includes forming an Al layer.

6. The method of claim 5, wherein implanting one of Si, C, and Ge includes implanting Ge into the remaining portion of the Al layer.

7. A method of fabricating a semiconductor device comprising:

providing a semiconductor substrate;

forming a gate stack on the substrate, the gate stack including an interfacial layer, a dielectric layer, and a polysilicon layer;

removing the polysilicon layer in the gate stack thereby forming a trench, the trench including the dielectric layer;

depositing a first metal layer over the substrate partially filling the trench;

depositing a second metal layer over the first metal layer filling a remainder of the trench;

performing a chemical mechanical polishing (CMP) to remove portions of the first and second metal layers outside the trench;

incorporating Si into the second metal layer during the deposition of the second metal layer or after performing the CMP.

8. The method of claim 7, wherein depositing the second metal layer includes performing a chemical vapor deposition (CVD) process;

wherein incorporating Si includes providing a Si precursor in the CVD process.

9. The method of claim 7, wherein depositing the second metal layer includes performing a physical vapor deposition (PVD) process;

wherein incorporating Si includes providing a sputtering target containing Si atoms.

10. The method of claim 7, wherein incorporating Si includes implanting Si after performing the CMP, the implantation utilizing an energy ranging from about 2 keV to about 7 keV and a dosage ranging from about 1E15 atoms/cm² to about 1E16 atoms/cm².

11. The method of claim 10, further comprising performing an annealing after the implantation, the annealing being performed at a temperature ranging from about 200°

C. to about 400°

C.

12. The method of claim 7, wherein incorporating Si includes incorporating Si such that the Si in the second metal layer, measured in atoms/cm³, has a percentage ranging from about 1E-5 to about 1E-8.

13. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming a gate structure on the substrate, the gate structure including a dummy electrode and a barrier layer;

removing the dummy electrode from the gate structure thereby forming a trench, such that the barrier layer remains within the trench;

forming a work function metal layer partially filling the trench;

forming an Al layer filling a remainder of the trench;

performing a chemical mechanical polishing (CMP) to remove portions of the work function metal layer and Al layer outside the trench; and

incorporating one of Si, C, and Ge into the Al layer during formation of the Al layer or after the CMP.

14. The method of claim 13, wherein incorporating one of Si, C, and Ge includes incorporating one of Si, C, and Ge such that the one of Si, C, and Ge in the Al layer, measured in atoms/cm³, has a percentage ranging from about 1E-5 to about 1E-8.

15. The method of claim 13, wherein incorporating one of Si, C, and Ge includes implanting the one of Si, C, and Ge into the Al layer after the CMP.

16. The method of claim 15, wherein the implantation utilizes an energy ranging from about 2 keV to about 7 keV and a dosage ranging from about 1E15 atoms/cm² to about 1E16 atoms/cm².

17. The method of claim 15, further comprising performing an annealing after the implantation, the annealing being performed at a temperature ranging from about 200°

C. to about 400°

C.

18. The method of claim 13, wherein incorporating one of Si, C, and Ge includes incorporating the one of Si, C, and Ge during a chemical vapor deposition or physical vapor deposition of the Al layer.

19. The method of claim 13, wherein incorporating one of Si, C, and Ge includes incorporating Si into the Al layer.

20. The method of claim 13, wherein forming the gate structure includes:

forming an interfacial layer on the substrate;

forming a high-k dielectric layer on the interfacial layer;

forming the barrier layer on the high-k dielectric layer;

forming a polysilicon layer on the barrier layer; and

patterning the interfacial layer, high-k dielectric layer, barrier layer, and polysilicon layer to form the gate structure, wherein the patterned polysilicon layer serves as the dummy electrode.