Interconnect barrier structure and method

• US 8,835,313 B2
• Filed: 08/02/2013
• Issued: 09/16/2014
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, I, Chen-Hua, Chiou, Wen-Chih, Wu, Tsang-Jiuh
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US13/957,685
• Publication Number:
  US 20130316528A1
• Time in Patent Office: 410 Days
• Field of Search: 438/667, 438/637, 438/643
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/15788 Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a first opening in a substrate, the substrate comprising a first side and a second side opposite the first side;

depositing a first barrier layer in the first opening using a first process, wherein the first process has a first step coverage;

filling a remainder of the first opening with a conductive material;

forming a dielectric layer over the conductive material;

forming a second opening in the conductive material to expose at least a portion of the conductive material, the second opening having a different width than the first opening;

depositing a second barrier layer in the second opening and in contact with the conductive material using a second process, wherein the second process has a second step coverage smaller than the first step coverage;

grinding the second side of the substrate to expose the conductive material; and

depositing a third barrier layer in physical contact with the conductive material within the opening using a third process, wherein the third process has a third step coverage different from the first step coverage.

2. The method of claim 1, wherein the first barrier layer comprises a first material and the second barrier layer comprises a second material different from the first material.

3. The method of claim 1, wherein the first barrier layer is a composite barrier layer.

4. The method of claim 3, wherein the depositing the first barrier layer further comprises:

depositing a layer of titanium; and

depositing a layer of titanium nitride.

5. The method of claim 1, wherein the first process is chemical vapor deposition and the second process is physical vapor deposition.

6. The method of claim 5, wherein the third process is physical vapor deposition.

7. The method of claim 1, further comprising forming a conductive connector adjacent to the third barrier layer.

8. The method of claim 7, wherein the forming the conductive connector comprises forming a copper pillar.

9. The method of claim 7, wherein the forming the conductive connector comprising forming a redistribution layer.

10. A method of manufacturing a semiconductor device, the method comprising:

depositing a first dielectric layer over a substrate, the substrate having a first side and a second side;

removing portions of the first dielectric layer to form a first opening with a first width;

removing portions of the substrate through the first opening to form a second opening with a second width less than the first width;

depositing a first barrier layer lining the first opening and the second opening, wherein the depositing the first barrier layer is performed at least in part using a first deposition process;

filling a remainder of the first opening and the second opening with a conductive material;

removing a portion of the second side of the substrate to expose the conductive material; and

depositing a second barrier layer in contact with the conductive material within the second opening and the second side of the substrate, wherein the depositing the second barrier layer is performed at least in part using a second deposition process different from the first deposition process.

11. The method of claim 10, wherein the substrate further comprises a second dielectric layer adjacent the first dielectric layer.

12. The method of claim 10, wherein the depositing the first barrier layer further comprises depositing a composite barrier layer.

13. The method of claim 12, wherein the depositing the composite barrier layer further comprises:

depositing a layer of titanium; and

depositing a layer of titanium nitride.

14. The method of claim 10, further comprising a conductive connector adjacent to the second barrier layer.

15. The method of claim 14, wherein the conductive connector is a redistribution layer.

16. The method of claim 10, wherein the first deposition process is a chemical vapor deposition process and the second deposition process is a physical vapor deposition process.

17. A method of manufacturing a semiconductor device, the method comprising:

forming an opening partially through a substrate;

lining the opening with a first barrier layer using a first deposition process with a first step coverage;

overfilling the opening with a conductive material;

planarizing the conductive material with the substrate;

depositing a planar second barrier layer in physical contact with the conductive material, the depositing the second barrier layer being performed at least in part with a second deposition process with a second step coverage less than the first step coverage;

removing a portion of the substrate opposite the second barrier layer to expose the conductive material, the conductive material being planar with the substrate; and

depositing a planar third barrier layer in physical contact with the conductive material, the depositing the planar third barrier layer being performed at least in part with a third deposition process with a third step coverage less than the first step coverage.

18. The method of claim 17, wherein the forming the first process is a chemical vapor deposition process.

19. The method of claim 18, wherein the second process is a physical vapor deposition process.

20. The method of claim 17, wherein the forming the first barrier layer further comprises:

forming a layer of titanium; and

forming a layer of titanium nitride.