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Interconnect barrier structure and method

  • US 8,835,313 B2
  • Filed: 08/02/2013
  • Issued: 09/16/2014
  • Est. Priority Date: 07/01/2011
  • Status: Active Grant
First Claim
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1. A method of manufacturing a semiconductor device, the method comprising:

  • forming a first opening in a substrate, the substrate comprising a first side and a second side opposite the first side;

    depositing a first barrier layer in the first opening using a first process, wherein the first process has a first step coverage;

    filling a remainder of the first opening with a conductive material;

    forming a dielectric layer over the conductive material;

    forming a second opening in the conductive material to expose at least a portion of the conductive material, the second opening having a different width than the first opening;

    depositing a second barrier layer in the second opening and in contact with the conductive material using a second process, wherein the second process has a second step coverage smaller than the first step coverage;

    grinding the second side of the substrate to expose the conductive material; and

    depositing a third barrier layer in physical contact with the conductive material within the opening using a third process, wherein the third process has a third step coverage different from the first step coverage.

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