Semiconductor device

• US 8,835,918 B2
• Filed: 09/10/2012
• Issued: 09/16/2014
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Isobe, Atsuo, Sasaki, Toshinari
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US13/608,039
• Publication Number:
  US 20130069053A1
• Time in Patent Office: 736 Days
• Field of Search: 257/43, 257/E29.273
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

To provide a transistor which includes an oxide semiconductor and is capable of operating at high speed or a highly reliable semiconductor device including the transistor, a transistor in which an oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer, which is embedded in a base insulating layer and whose upper surface is at least partly exposed from the base insulating layer, and a wiring layer provided above the oxide semiconductor layer is electrically connected to the electrode layer or a part of a low-resistance region of the oxide semiconductor layer, which overlaps with the electrode layer.

Claims

1. A semiconductor device comprising:

a base insulating layer;

a first conductive layer and a second conductive layer embedded in the base insulating layer;

an oxide semiconductor layer including a channel formation region, the oxide semiconductor layer provided on and in contact with the first conductive layer, the second conductive layer, and the base insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the channel formation region with the gate insulating layer therebetween;

an insulating layer over the gate insulating layer; and

a first wiring layer and a second wiring layer electrically connected to the first conductive layer and the second conductive layer, respectively, through openings provided in the insulating layer and the gate insulating layer,

wherein the openings do not overlap with the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the first wiring layer and the second wiring layer are in contact with the first conductive layer and the second conductive layer, respectively, through the openings provided in the insulating layer and the gate insulating layer.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer includes a pair of low-resistance regions,

wherein the channel formation region is between the pair of low-resistance regions, and

wherein in the pair of low-resistance regions, one low-resistance region is in contact with the first conductive layer and the other low-resistance region is in contact with the second conductive layer.

4. The semiconductor device according to claim 3, wherein the pair of low-resistance regions includes at least one of P, As, Sb, B, Al, N, Ar, He, Ne, In, F, Cl, Ti and Zn as a dopant.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes indium, gallium, and zinc.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has crystallinity.

7. A memory cell comprising the semiconductor device according to claim 1.

8. A semiconductor device comprising:

a transistor, wherein a first channel formation region of the transistor comprises silicon;

a first insulating layer over the transistor;

a first conductive layer and a second conductive layer over the transistor;

an oxide semiconductor layer including a second channel formation region, the oxide semiconductor layer provided on and in contact with the first conductive layer, the second conductive layer, and the first insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the second channel formation region with the gate insulating layer therebetween;

a second insulating layer over the gate insulating layer; and

a first wiring layer and a second wiring layer electrically connected to the first conductive layer and the second conductive layer, respectively, through openings provided in the second insulating layer and the gate insulating layer,

wherein the openings do not overlap with the oxide semiconductor layer.

9. The semiconductor device according to claim 8,

wherein the oxide semiconductor layer includes a pair of low-resistance regions,

wherein the second channel formation region of the oxide semiconductor layer is between the pair of low-resistance regions, and

wherein in the pair of low-resistance regions, one low-resistance region is in contact with the first conductive layer and the other low-resistance region is in contact with the second conductive layer.

10. The semiconductor device according to claim 9, wherein the pair of low-resistance regions includes at least one of P, As, Sb, B, Al, N, Ar, He, Ne, In, F, Cl, Ti and Zn as a dopant.

11. The semiconductor device according to claim 8, wherein the oxide semiconductor layer includes indium, gallium, and zinc.

12. The semiconductor device according to claim 8, wherein the oxide semiconductor layer has crystallinity.

13. A memory cell comprising the semiconductor device according to claim 8.

14. The semiconductor device according to claim 8, wherein the first conductive layer and the second conductive layer are embedded in the first insulating layer.