Planar SRFET using no additional masks and layout method
First Claim
1. A semiconductor power device supported on a semiconductor substrate of a first conductivity type having a bottom layer functioning as a bottom electrode and an epitaxial layer overlying said bottom layer having a same conductivity type as said bottom layer, said semiconductor power device comprising a plurality of FET cells whereas each cell further comprising:
- a plurality of FET cells wherein each FET cell further comprises a body region of a second conductivity type extending vertically from a top surface into said epitaxial layer and laterally surrounding outer edges of each of the FET cells underneath a planar insulated gate disposed substantially in a central portion of the FET cell on the top surface of the semiconductor substrate;
each of said FET cells further includes a source region of the first conductivity type encompassed in said body region immediately under and laterally surrounding outer edges of said planar insulated gate;
each of said FET cells further includes a heavy body dopant region of said second conductivity type encompassed in said body region and disposed underneath and extends outwardly toward and terminates before reaching the outer edges of the FET cells thus forming a Schottky pocket near the top surface of the semiconductor substrate in said body region;
a thin layer composed of a narrow bandgap material disposed on the top surface of said epitaxial layer and extended laterally between source regions of two adjacent FET cells; and
a Schottky metal layer overlaying the top surface of the epitaxial layer covering over the thin layer of the narrow bandgap material and extends laterally from an outer edges of the source region across an area of the top surface of the semiconductor substrate over the heavy body dopant region and the Schottky pocket in of the body region near the top surface of the semiconductor substrate surrounding the heavy body dopant region, wherein said Schottky metal layer further extending over an area on the top surface of the semiconductor substrate across an open substrate region between two of said FET cells and then further extends to the outer edge of the source region of another FET cell thus forming an integrated Schottky junction diode for the FET cells.
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Abstract
A semiconductor power device is supported on a semiconductor substrate with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.
7 Citations
2 Claims
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1. A semiconductor power device supported on a semiconductor substrate of a first conductivity type having a bottom layer functioning as a bottom electrode and an epitaxial layer overlying said bottom layer having a same conductivity type as said bottom layer, said semiconductor power device comprising a plurality of FET cells whereas each cell further comprising:
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a plurality of FET cells wherein each FET cell further comprises a body region of a second conductivity type extending vertically from a top surface into said epitaxial layer and laterally surrounding outer edges of each of the FET cells underneath a planar insulated gate disposed substantially in a central portion of the FET cell on the top surface of the semiconductor substrate; each of said FET cells further includes a source region of the first conductivity type encompassed in said body region immediately under and laterally surrounding outer edges of said planar insulated gate; each of said FET cells further includes a heavy body dopant region of said second conductivity type encompassed in said body region and disposed underneath and extends outwardly toward and terminates before reaching the outer edges of the FET cells thus forming a Schottky pocket near the top surface of the semiconductor substrate in said body region; a thin layer composed of a narrow bandgap material disposed on the top surface of said epitaxial layer and extended laterally between source regions of two adjacent FET cells; and a Schottky metal layer overlaying the top surface of the epitaxial layer covering over the thin layer of the narrow bandgap material and extends laterally from an outer edges of the source region across an area of the top surface of the semiconductor substrate over the heavy body dopant region and the Schottky pocket in of the body region near the top surface of the semiconductor substrate surrounding the heavy body dopant region, wherein said Schottky metal layer further extending over an area on the top surface of the semiconductor substrate across an open substrate region between two of said FET cells and then further extends to the outer edge of the source region of another FET cell thus forming an integrated Schottky junction diode for the FET cells. - View Dependent Claims (2)
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Specification