Memory device with recessed construction between memory constructions

• US 8,836,023 B2
• Filed: 02/10/2011
• Issued: 09/16/2014
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US13/025,047
• Publication Number:
  US 20110133270A1
• Time in Patent Office: 1,314 Days
• Field of Search: 257/301, 257329-333, 257/520, 257/E29.257, 257/E29.26
• US Class Current: 257/331
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.

Claims

1. A memory device comprising:

a substrate having a first surface and a doping concentration;

a plurality of memory cells arranged in a pattern on the substrate, wherein the plurality of memory cells each include a charge storage device and a recessed access device formed so as to extend into the substrate, wherein the recessed access device is configured to induce a first depletion region in the substrate and define a current flow path about the recessed perimeter of the recessed access device within the substrate; and

a plurality of isolation structures each recessed in the substrate so as to isolate adjacent memory cells of the plurality of memory cells from each other, wherein each of the plurality of isolation structures receives a bias voltage during operation of the memory device that together with the doping concentration of the substrate induces a second depletion region in the substrate that merges with the corresponding first depletion region to thereby inhibit leakage between adjacent memory cells.

2. The memory device of claim 1, wherein each of the plurality of memory cells further comprises a digit line, wherein the charge storage device is formed on the first surface of the substrate, and wherein the recessed access device comprises a recessed access transistor having a gate formed so as to extend into the substrate.

3. The memory device of claim 2, wherein the recessed access transistor further includes a pair of source/drain regions formed adjacent the first surface of the substrate and wherein the recessed access transistor includes a gate structure that extends inward from the first surface into the substrate such that activation of the gate results in the formation of a conductive channel so that current flows between the two source/drain regions.

4. The device of claim 2, wherein the plurality of isolation structures comprise a plurality of gate structures that are formed so as to extend into the substrate from the first surface and wherein the plurality of gate structures are grounded.

5. The device of claim 4, wherein the second depletion region merges with the corresponding first depletion region such that the doping level of the substrate can be reduced without increasing the leakage current between memory cells.

6. The device of claim 3, wherein each of the plurality of memory cells comprise a first and a second plurality of recessed gates and a first and a second charge storage device and wherein each of the plurality of memory cells include a common source/drain region that is common between the first and second gates and is electrically coupled to a single digit line.

7. The device of claim 6, further comprising a plurality of source/drain regions that are electrically coupled to the charge storage device.

8. The device of claim 1, wherein the substrate comprises a p-doped substrate and wherein the plurality of recessed gates comprises recessed access devices.

9. The device of claim 1, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each memory cell defines an active area.

10. The device of claim 9, wherein the active area of each of the plurality of cells is oriented at an angle of about 45 degrees with respect to the bit line and word line.

11. A memory device comprising:

a substrate having a first surface and a doping concentration;

a first memory construction comprising;

a first memory storage device;

a first digit line; and

a first transistor construction having a first recessed gate that extends into the substrate from the first surface, a first source, and a first drain, wherein the first memory storage device is electrically coupled to the first source, and the first digit line is electrically coupled to the first drain;

a second memory construction comprising;

a second memory storage device;

a second digit line; and

a second transistor construction having a second recessed gate, a second source, and a second drain, wherein the second memory storage device is electrically coupled to the second source, and the second digit line is electrically coupled to the second drain;

wherein the first and second transistor constructions are recessed access devices; and

a grounded recessed transistor gate construction interposed between the first and second memory constructions, wherein during operation of the memory device the grounded recessed gate construction receives a bias that together with the doping concentration of the substrate forms a depletion region that merges with a depletion region of the first transistor construction and a depletion region of the second transistor construction such that leakage current between the first transistor construction and the second transistor construction is substantially reduced.

12. The memory device of claim 11, wherein the first and second transistor constructions are two-sided access transistors.

13. The memory device of claim 11, wherein the memory device is a 4.5F2 DRAM cell.

14. The memory device of claim 11, wherein the first digit line and the second digit line are the same.

15. The device of claim 11, wherein substrate is a semiconductor substrate, and wherein the depletion region of the grounded recessed transistor gate construction merges with the depletion region of the first transistor construction and the depletion region of the second transistor construction such that the doping level of the semiconductor substrate can be reduced without substantially increasing leakage current between the first transistor construction and the second transistor construction.

16. A memory device comprising:

a substrate having a first surface and a doping concentration;

a first memory construction comprising;

a first transistor construction having a first recessed gate that extends into the substrate from the first surface;

a first source; and

a first drain, the first recessed gate interposed between the first source and the first drain;

a second memory construction comprising;

a second transistor construction having a second recessed gate that extends into the substrate from the first surface;

a second source; and

a second drain, the second recessed gate interposed between the second source and the second drain; and

a recessed transistor gate construction interposed between the first and second memory constructions, wherein during operation of the memory device the recessed transistor gate construction receives a bias that together with the doping concentration of the substrate forms a depletion region that merges with a depletion region of the first transistor construction and a depletion region of the second transistor construction to provide isolation between the first memory construction and the second memory construction.

17. The device of claim 16, wherein the recessed transistor gate construction is biased such that the recessed transistor gate construction is in the depletion mode.

18. The device of claim 16, wherein the recessed transistor gate construction is biased such that the recessed transistor gate construction is in the accumulation mode.

19. The device of claim 16, wherein the recessed transistor gate construction is grounded.

20. The device of claim 16, further comprising a first memory storage device electrically coupled to the first source and a first digit line electrically coupled to the first drain.

21. The device of claim 16, further comprising a second memory storage device electrically coupled to the second source and a second digit line electrically coupled to the second drain.

22. The device of claim 16, wherein substrate is a semiconductor substrate, and wherein the depletion region of the recessed transistor gate construction merges with the depletion region of the first transistor construction and the depletion region of the second transistor construction such that the doping level of the semiconductor substrate can be reduced without substantially increasing leakage current between the first transistor construction and the second transistor construction.