Electronic device including a trench and a conductive structure therein having a contact within a Schottky region and a process of forming the same

• US 8,836,024 B2
• Filed: 03/20/2012
• Issued: 09/16/2014
• Est. Priority Date: 03/20/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Padmanabhan, Balaji, Sellers, James
• Primary Examiner(s): Fulk, Steven J
• Application Number:
  US13/425,030
• Publication Number:
  US 20130248992A1
• Time in Patent Office: 910 Days
• Field of Search: 257/334, 257/E29.26, 257/E21.419, 438/272
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate, wherein the patterned semiconductor layer defines first and second trenches. The electronic device can also include a first conductive structure within the first trench, a gate electrode within the first trench and overlying the first conductive structure, a first insulating member within the second trench, and a second conductive structure within the second trench. The second conductive structure can include a first portion and a second portion overlying the first portion, the first insulating member can be disposed between the patterned semiconductor layer and the first portion of the second conductive structure; and the second portion of the second conductive structure can contact the patterned semiconductor layer at a Schottky region. Processes of forming the electronic device can take advantage of integrating formation of the Schottky region into a contact process flow.

Claims

1. An electronic device comprising a transistor structure, comprising:

a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate;

a first conductive structure within the first trench;

a gate electrode within the first trench and overlying the first conductive structure;

a first insulating member within the second trench; and

a second conductive structure within the second trench, wherein;

the second conductive structure includes a first portion and a second portion overlying the first portion;

the first insulating member is disposed between the patterned semiconductor layer and the first portion of the second conductive structure; and

the second portion of the second conductive structure contacts the patterned semiconductor layer at a Schottky region.

2. The electronic device of claim 1, wherein the first trench is wider than the second trench.

3. The electronic device of claim 1, wherein, within the second trench, the first portion of the second conductive structure is narrower than the second portion of the second conductive structure.

4. The electronic device of claim 1, further comprising:

a body region disposed over the Schottky region;

a second insulating member disposed between the first conductive structure and patterned semiconductor layer; and

a gate dielectric layer disposed between the gate electrode and the body region, wherein the gate dielectric layer is thinner than the second insulating member.

5. The electronic device of claim 4, further comprising:

a source region disposed over the body region; and

a body contact region within the body region and adjacent to the second trench,

wherein the second conductive structure directly contacts the source region and the body contact region.

6. The electronic device of claim 1, further comprising:

another first trench defined by the patterned semiconductor layer; and

another gate electrode within the other first trench,

wherein the second trench and second conductive structure are disposed between the first trenches and first gate electrodes.

7. The electronic device of claim 1, wherein the first portion of the second conductive structure and the second portion of the second conductive structure comprise different materials.

8. The electronic device of claim 7, wherein:

the first portion comprises doped polycrystalline silicon; and

the second portion comprises tungsten.

9. The electronic device of claim 1, further comprising a second insulating member between the first conductive structure and the gate electrode, wherein, in a finished device, the first conductive structure and the second conductive structure are electrically connected to each other.

10. A process of forming an electronic device comprising:

providing a workpiece including a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface;

patterning the semiconductor layer to define a first trench that extends from the primary surface towards the substrate;

forming a first conductive structure within the first trench;

forming a gate electrode within the first trench after forming the first conductive structure;

patterning the semiconductor layer to define a second trench that extends from the primary surface towards the substrate;

forming a first insulating member within the second trench; and

forming a second conductive structure within the second trench after forming the first insulating member, wherein;

the second conductive structure includes a first portion and a second portion overlying the first portion;

the first insulating member is disposed between the patterned semiconductor layer and the first portion of the second conductive structure; and

the second portion of the second conductive structure contacts the patterned semiconductor layer at a Schottky region.

11. The process of claim 10, wherein:

patterning the semiconductor layer to define the first trench defines another first trench;

forming the gate electrode forms another gate electrode within the other first trench; and

the second conductive structure is disposed within the semiconductor layer between the gate electrodes.

12. The process of claim 10, wherein forming the first insulating member comprises:

forming a first insulating layer within the second trench; and

removing a portion of the first insulating layer to form the first insulating member, wherein substantially all of the first insulating member within the second trench lies at an elevation below the primary surface.

13. The process of claim 10, further comprising forming a body region within the semiconductor layer, wherein after forming the second conductive structure, the Schottky region is disposed at an elevation between the body region and the first insulating member.

14. The process of claim 13, wherein the Schottky region extends no greater than approximately 50% of the distance between a bottom of the body region and a bottom of the second trench.

15. The process of claim 13, further comprising forming a contact opening after forming the gate electrode, wherein patterning the semiconductor layer to define the second trench is performed after forming the contact opening.

16. The process of claim 15, further comprising:

forming a source region, wherein in a finished device, the body region is disposed between the source region and the substrate; and

doping a portion of the semiconductor layer adjacent to the second trench to form a body contact region within the body region.

17. The process of claim 15, wherein:

patterning the semiconductor layer to define the second trench comprises etching a first portion of the semiconductor layer to expose a portion of the body region along the second trench before forming the body contact region; and

patterning the semiconductor layer to define the second trench further comprises etching a second portion of the semiconductor layer such that the second trench extends to a depth below the body region, wherein etching the second portion is performed after forming the body contact region.

18. The process of claim 13, wherein the second portion of the second conductive structure directly contacts the source region, the body contact region, and the semiconductor layer below the body region.

19. The process of claim 18, further comprising electrically connecting the first and second conductive structures to each other.

20. The process of claim 10, wherein:

the first trench extends to a first depth as measured from the primary surface;

the second trench extends to a second depth as measured from the primary surface; and

the second depth is within approximately 20% of the first depth.