Superjunction structures for power devices and methods of manufacture

• US 8,836,028 B2
• Filed: 04/27/2011
• Issued: 09/16/2014
• Est. Priority Date: 04/27/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Rinehimer, Mark L., Shenoy, Praveen Muraleedharan, Lee, Jaegil, Reichl, Dwayne S., Heidenreich, Harold
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/095,690
• Publication Number:
  US 20120273884A1
• Time in Patent Office: 1,238 Days
• Field of Search: 257/341, 257/120, 257/E29.262, 257/E21.41, 257/330, 257/332, 257/338, 257/339, 257/340, 257/342, 438/268, 438/270, 438/259
• US Class Current: 257/341
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

Claims

1. A power device comprising:

at least one N-type epitaxial layer disposed on a substrate;

a plurality of trenches extending into the at least one N-type epitaxial layer, the plurality of trenches being filled with a P-type silicon material, the P-type silicon material in the plurality of trenches defining P-pillars, portions of the at least one N-type epitaxial layer separating the P-pillars defining N-pillars, such that the N-pillars and the P-pillars define alternating P-N-pillars;

an active region; and

a termination region surrounding the active region, the alternating P-N-pillars being disposed in both the active region and the termination region, the termination region including a predetermined number of floating P-pillars, each N-pillar located between two adjacent floating P-pillars of the predetermined number of floating P-pillars including an N-type surface region disposed along an upper surface, the N-type surface region having a lower doping concentration than a doping concentration of a remaining portion of the N-pillar in which the N-type surface region is disposed.

2. The power device of claim 1, further comprising:

a P-type body region disposed in the at least one N-type epitaxial layer;

a gate electrode adjacent to but insulated from the P-type body region;

an N-type source region disposed in the P-type body region;

a source metal electrically contacting the source region; and

a P-Iso region disposed on a surface of the at least one N-type epitaxial layer, at least two P-pillars of the alternating P-N-pillars in the termination region being electrically connected to the source metal via the P-Iso region.

3. The power device of claim 2, further comprising:

a shallow trench extending into the at least one N-type epitaxial layer; and

a gate dielectric layer lining a sidewall of the shallow trench, the gate electrode being disposed in the shallow trench.

4. The power device of claim 2, wherein the gate electrode includes a planar gate electrode disposed on but insulated from the at least one N-type epitaxial layer by a gate dielectric layer.

5. The power device of claim 1, wherein each of at least two P-pillars of the alternating P-N-pillars in the termination region includes a P-type enrichment region disposed along an upper surface, the P-type enrichment region having a higher doping concentration than a doping concentration of a remaining portion of the P-pillar in which the P-type enrichment region is disposed.

6. The power device of claim 5, further comprising:

a P-type body region disposed in the at least one N-type epitaxial layer;

a gate electrode adjacent to but insulated from the P-type body region;

an N-type source region disposed in the P-type body region;

a source metal electrically contacting the source region; and

a P-Iso region disposed along a surface of the at least one N-type epitaxial layer, at least two P-pillars of the alternating P-N-pillars in the termination region being electrically connected to the source metal via the P-Iso region.

21. The power device of claim 4, wherein the planar gate electrode is a first planar gate electrode, the power device further comprising:

a second planar gate electrode laterally spaced from the first planar gate electrode, at least one trench of the plurality of trenches being disposed between the first planar gate electrode and the second planar gate electrode.

7. A power device comprising:

at least one N-type epitaxial layer disposed on a substrate;

a plurality of trenches extending into the at least one N-type epitaxial layer, the plurality of trenches being filled with a P-type silicon material, the P-type silicon material in the plurality of trenches defining P-pillars, portions of the at least one N-type epitaxial layer separating the P-pillars defining N-pillars, such that the N-pillars and the P-pillars define alternating P-N-pillars;

an active region; and

a termination region surrounding the active region, the alternating P-N-pillars being disposed in both the active region and the termination region, the alternating P-N-pillars in the termination region concentrically surrounding the active region and Including at least two floating P-pillars, each of the at least two floating P-pillars including a P-type ring disposed in an upper portion;

a plurality of field plates disposed in the termination region, disposed on but insulated from the at least one N-type epitaxial layer, the plurality of field plates concentrically surrounding the active region; and

a plurality of contacts, a contact of the plurality of contacts electrically connecting a field plate of the plurality of field plates and at least one of the P-type rings, the plurality of contacts being disposed directly above a corresponding floating P-pillar of the at least two floating P-pillars.

8. The power device of claim 7, wherein the at least two floating P-pillars are electrically contacted at locations of the at least two floating P-pillars that define a respective corner.

9. The power device of claim 7, wherein a width of the P-type rings gradually decreases in a direction away from the active region.

10. The power device of claim 7, wherein each of the plurality of field plates is disposed directly above a corresponding floating P-pillar of the at least two floating P-pillars and directly above an N-pillar adjacent to the corresponding floating P-pillar.

11. The power device of claim 7, wherein the plurality of contacts are disposed through at least one insulating layer that is disposed between the plurality of field plates and the at least one N-type epitaxial layer.

12. The power device of claim 7, wherein adjacent P-pillars of the P-pillars in the active and termination regions are equally spaced.

13. The power device of claim 7, wherein the P-type rings are centered about a corresponding floating P-pillar of the at least two floating P-pillars.

14. The power device of claim 7, wherein each P-type ring includes a highly doped P+ region that defines an electrical contact between at least one of the plurality of field plates and the P-type ring.

15. A power device comprising:

an active region;

a termination region surrounding the active region;

a plurality of stripe-shaped pillars of alternating conductivity type disposed in and extending through the active region; and

a plurality of octagon-shaped pillars of alternating conductivity type disposed in and extending through the termination region, the plurality of octagon-shaped pillars concentrically surrounding the active region.

16. The power device of claim 15, wherein corner edges of the plurality of octagon-shaped pillars of alternating conductivity type gradually increase in length in a direction away from the active region.

17. The power device of claim 15, wherein the plurality of stripe-shaped pillars includes a plurality of stripe-shaped P-pillars, and the plurality of octagon-shaped pillars includes a plurality of octagon-shaped P-pillars, ends of the plurality of stripe-shaped P-pillars being spaced from the plurality of octagon-shaped P-pillars by a gap region that electrically floats.

18. The power device of claim 15, wherein a first four of eight legs of each of the plurality of octagon-shaped pillars have a different length than a second four legs of the eight legs, the second four legs being different than the first four legs.

19. The power device of claim 15, further comprising a plurality of trenches extending into at least one epitaxial layer of a first conductivity type, the plurality of trenches having a silicon material of a second conductivity type disposed therein, the silicon material of the second conductivity type disposed in the plurality of trenches, together with portions of the at least one epitaxial layer separating the plurality of trenches from one another, defining the plurality of octagon-shaped pillars of alternating conductivity type, sidewalls of the plurality of trenches along all eight legs of the plurality of octagon-shaped pillars having a same plane direction.

20. The power device of claim 15, further comprising:

a body region of a first conductivity type disposed in the at least one epitaxial layer;

a source region of a second conductivity type disposed in the body region; and

a gate electrode extending adjacent to but being insulated from the body region, the gate electrode overlapping a portion of the source region.