Semiconductor structure and process thereof

• US 8,836,049 B2
• Filed: 06/13/2012
• Issued: 09/16/2014
• Est. Priority Date: 06/13/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsai, Min-Chuan, Huang, Hsin-Fu, Hsu, Chi-Mao, Lin, Chin-Fu, Chen, Chien-Hao, Chen, Wei-Yu, Sun, Chi-Yuan, Hsieh, Ya-Hsueh, Cheng, Tsun-Min
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US13/495,009
• Publication Number:
  US 20130334690A1
• Time in Patent Office: 825 Days
• Field of Search: 257/412, 257/751, 257/E29.16, 257/E21.179, 438/592, 438/590
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.

Claims

1. A semiconductor structure, comprising:

a work function metal layer located on a substrate, the work function metal layer comprising titanium aluminide, regardless of whether the semiconductor structure is a PMOS transistor or a NMOS transistor;

a work function metal oxide layer located on the work function metal layer;

a main electrode located on the work function metal oxide layer; and

a barrier-wetting layer located between the work function metal oxide layer and the main electrode, so that the work function metal layer, the work function metal oxide layer, the barrier-wetting layer and the main electrode constitute a metal gate.

2. The semiconductor structure according to claim 1, wherein the work function metal oxide layer comprises an aluminum titanium oxide layer.

3. The semiconductor structure according to claim 1, wherein the main electrode comprises aluminum.

4. The semiconductor structure according to claim 1, wherein the barrier-wetting layer comprises a titanium nitride/titanium layer.

5. The semiconductor structure according to claim 4, wherein a top layer is the titanium layer and a bottom layer is the titanium nitride layer.

6. The semiconductor structure according to claim 1, wherein the barrier-wetting layer comprises a titanium/titanium nitride/titanium layer.

7. A semiconductor structure, comprising:

a work function metal layer located on a substrate, the work function metal layer comprising titanium aluminide, regardless of whether the semiconductor structure is a PMOS transistor or a NMOS transistor;

a metal oxide layer located on the work function metal layer;

a main electrode located on the metal oxide layer; and

a barrier-wetting layer located between the metal oxide layer and the main electrode, so that the work function metal layer, the metal oxide layer, the barrier-wetting layer and the main electrode constitute a metal gate.

8. The semiconductor structure according to claim 7, wherein the metal oxide layer comprises an aluminum titanium oxide layer.

9. The semiconductor structure according to claim 7, wherein the main electrode comprises aluminum.

10. The semiconductor structure according to claim 7, wherein the barrier-wetting layer comprises a titanium nitride/titanium layer.

11. The semiconductor structure according to claim 7, wherein the barrier-wetting layer comprises a titanium/titanium nitride/titanium layer.

12. The semiconductor structure according to claim 10, wherein a top layer is the titanium layer and a bottom layer is the titanium nitride layer.