Structure and method to fabricate a body contact

• US 8,836,050 B2
• Filed: 01/24/2013
• Issued: 09/16/2014
• Est. Priority Date: 11/11/2010
• Status: Expired due to Fees

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Pei, Chengwen, Booth, Roger Allen, Cheng, Kangguo, Ervin, Joseph, Todi, Ravi M., Wang, Geng
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US13/748,942
• Publication Number:
  US 20130134527A1
• Time in Patent Office: 600 Days
• Field of Search: 257/347, 257/401, 257/413, 257/751, 257/755, 257/774, 257/778
• US Class Current: 257/413
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

Claims

1. A semiconductor structure comprising:

a dielectric layer;

a transistor, the transistor comprising a body, source, drain, and gate, wherein the transistor is disposed on the dielectric layer;

a void formed in the dielectric layer, thereby exposing the body of the transistor, wherein the body is disposed adjacent to the source, drain, and gate;

a silicide layer disposed in the void formed in the dielectric layer, and on the body of the transistor;

a polysilicon layer disposed on the silicide layer; and

a metal liner disposed on the silicide layer, such that the metal liner is between the silicide layer and the polysilicon layer.

2. The semiconductor structure of claim 1, further comprising:

at least one metal contact;

at least one via;

at least one active silicon area connected to a metal contact by a via;

wherein a second void is formed in the dielectric layer, thereby exposing the at least one active silicon area; and

wherein the silicide layer is also disposed on the at least one active silicon area.

3. The semiconductor structure of claim 2, further comprising a void formed in the polysilicon layer, the void disposed between the body of the transistor, and the at least one active silicon area connected to a metal contact by a via.

4. The semiconductor structure of claim 1, wherein the silicide layer comprises nickel silicide.

5. The semiconductor structure of claim 1, wherein the silicide layer comprises cobalt silicide.

6. The semiconductor structure of claim 1, wherein the metal liner is comprised of copper.

7. The semiconductor structure of claim 1, wherein the metal liner is comprised of titanium.