Vertically oriented inductor within interconnect structures and capacitor structure thereof

• US 8,836,078 B2
• Filed: 08/18/2011
• Issued: 09/16/2014
• Est. Priority Date: 08/18/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cho, Hsiu-Ying
• Primary Examiner(s): AHMED, SELIM U
• Application Number:
  US13/212,982
• Publication Number:
  US 20130043557A1
• Time in Patent Office: 1,125 Days
• Field of Search: 257/531, 257/E29.002, 257/22, 257/E21.022, 257/E21.158
• US Class Current: 257/531
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate having a horizontal surface. The semiconductor device includes an interconnect structure formed over the horizontal surface of the substrate. The interconnect structure includes an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The interconnect structure includes a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

Claims

1. A semiconductor device, comprising:

a substrate having a surface that is defined by an X axis and a Y axis that is perpendicular to the X axis;

an inductor disposed over the surface of the substrate, the inductor having a coil that is wound at least in part vertically about a Z axis that is perpendicular to the X axis and the Y axis; and

a capacitor disposed over the substrate and adjacent to the inductor.

2. The semiconductor device of claim 1, wherein the inductor and capacitor are disposed within an interconnect structure formed over the substrate.

3. The semiconductor device of claim 2, wherein the interconnect structure includes a plurality of conductive lines and a plurality of conductive vias, and wherein the inductor and the capacitor are each implemented using a respective subset of the conductive lines and conductive vias.

4. The semiconductor device of claim 3, wherein the conductive lines of the inductor are perpendicular to the conductive lines of the capacitor.

5. The semiconductor device of claim 1, wherein the inductor and the capacitor are interdigitated.

6. The semiconductor device of claim 1, wherein the inductor has an associated magnetic field that is substantially parallel to the surface of the substrate.

7. The semiconductor device of claim 1, wherein the surface of the substrate is a horizontal surface, and the winding orientation of the inductor is a vertical winding orientation.

8. The semiconductor device of claim 1, wherein the inductor and the capacitor are separated by a dielectric material.

9. The semiconductor device of claim 1, wherein the inductor and the capacitor are shielded by a shielding structure that includes a plurality of strip lines.

10. A semiconductor device, comprising:

a substrate having a horizontal surface; and

an interconnect structure formed over the horizontal surface of the substrate, the interconnect structure including;

an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate; and

a capacitor disposed proximate to the inductor coil, the capacitor having an anode component and a cathode component;

wherein the inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

11. The semiconductor device of claim 10, wherein:

the interconnect structure includes a plurality of metal lines disposed in a plurality of interconnect layers; and

the elongate members of the inductor coil and the elongate members of the capacitor each include a respective subset of the metal lines.

12. The semiconductor device of claim 11, wherein:

the interconnect structure further includes a plurality of via stacks; and

the inductor coil includes a subset of the via stacks that interconnect the elongate members of the inductor coil together.

13. The semiconductor device of claim 10, wherein at least some of the elongate members of the capacitor are surrounded by the inductor coil.

14. The semiconductor device of claim 10, wherein the elongate members of the inductor coil are perpendicular to the elongate members of the capacitor.

15. The semiconductor device of claim 10, wherein the elongate members of the anode component are interdigitated with the elongate members of the cathode component.

16. A semiconductor device, comprising:

a substrate having a relatively planar surface;

an interconnect structure over the relatively planar surface of the substrate, the interconnect structure having a plurality of conductive lines interconnected by a plurality of vias,

an inductor formed in the interconnect structure, having a coil winding that at least in part spans a vertical direction that is perpendicular to the relatively planar surface, and

a capacitor formed in the interconnect structure, having an anode component that is interdigitated with a cathode component.

17. The device of claim 16, wherein the interconnect structure forms an L-C tank.