Cost-effective TSV formation

• US 8,836,085 B2
• Filed: 09/04/2013
• Issued: 09/16/2014
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Ku-Feng, Lin, Yung-Chi, Chang, Hung-Pin, Wu, Tsang-Jiuh, Chiou, Wen-Chih
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US14/018,210
• Publication Number:
  US 20140008802A1
• Time in Patent Office: 377 Days
• Field of Search: 257/621, 257/773, 257/774, 257/775
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.

Claims

1. A device comprising:

a substrate comprising a first surface, and a second surface opposite the first surface;

a through-substrate via (TSV) extending from the first surface to the second surface of the substrate, wherein the TSV is formed of a continuous metallic material;

a dielectric liner between the TSV and the substrate, wherein the dielectric liner extends over the first surface of the substrate;

a dielectric layer over the substrate, wherein the dielectric layer is on a top surface of the dielectric liner; and

a first metal pad in the dielectric layer and physically contacting the TSV, wherein the first metal pad is formed of the continuous metallic material, wherein a top surface of the first metal pad is substantially coplanar with a top surface of the dielectric layer.

2. The device of claim 1, wherein the dielectric layer is on a same side of the substrate as the first surface, and wherein the device further comprises a barrier layer continuously extending from the top surface of the dielectric layer to the second surface of the substrate, with the barrier layer separating the TSV from the substrate.

3. The device of claim 1, wherein the substrate is a semiconductor substrate, and wherein no active device is formed at the first and the second surfaces of the substrate.

4. The device of claim 1, wherein the substrate is a dielectric substrate.

5. The device of claim 1 further comprising:

a second metal pad electrically coupled to the TSV, wherein the first and the second metal pads are on opposite sides of the substrate; and

a diffusion barrier layer formed of a material different from the continuous metallic material, wherein the diffusion barrier contacts the second metal pad and the TSV, and spaces the second metal pad apart from the TSV.

6. The device of claim 1, wherein the first metal pad has a horizontal dimension greater than a horizontal dimension of the TSV.

7. The device of claim 1 further comprising a metal line in the dielectric layer, wherein the metal line is over the dielectric liner.

8. A device comprising:

a substrate comprising a top surface, and a bottom surface opposite the top surface;

a through-substrate via (TSV) extending from the top surface of the substrate into the substrate;

an isolation layer over the top surface of the substrate;

a dielectric layer over the isolation layer;

a metal pad in the dielectric layer and contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and have different horizontal dimensions;

a conductive diffusion barrier extending from a top surface of the dielectric layer to a bottom surface of the TSV, wherein the conductive diffusion barrier encircles the metal pad and the TSV; and

a dielectric liner between the conductive diffusion barrier and the substrate, wherein the isolation layer is on a top surface of the dielectric liner.

9. The device of claim 8, wherein the conductive diffusion barrier comprises a material selected from the group consisting essentially of titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof.

10. The device of claim 8, wherein the conductive diffusion barrier does not extend to directly over, and vertically overlapping, the TSV.

11. The device of claim 8, wherein the dielectric liner does not extend to directly over the top surface of the substrate.

12. The device of claim 8, wherein the dielectric liner extends to directly over the top surface of the substrate.

13. The device of claim 8, wherein the same material is a copper-containing material.

14. A device comprising:

a semiconductor substrate comprising a top surface, and a bottom surface opposite the top surface;

a through-substrate via (TSV) extending from the top surface to the bottom surface of substrate;

a first dielectric layer over the semiconductor substrate;

a second dielectric layer over the first dielectric layer;

a first metal pad in the second dielectric layer and electrically coupled to the TSV, wherein the first metal pad and the TSV are formed of a same copper-containing material, and wherein the first metal pad has a horizontal dimension greater than a horizontal dimension of the TSV;

a diffusion barrier comprising a first sidewall portion on a sidewall of the first metal pad, and a second sidewall portion on a sidewall of the TSV; and

a dielectric liner between the diffusion barrier and the semiconductor substrate, wherein the first dielectric layer is on a top surface of the dielectric liner.

15. The device of claim 14, wherein the dielectric liner is between and contacting the second sidewall portion of the diffusion barrier and the semiconductor substrate.

16. The device of claim 14, wherein the dielectric liner extends to directly over and contacting the top surface of the semiconductor substrate.

17. The device of claim 14, wherein the dielectric liner does not extend to directly over and contacting the top surface of the semiconductor substrate.

18. The device of claim 14 further comprising a metal line in the second dielectric layer, and an additional diffusion barrier separating the metal line from the first and the second dielectric layers.

19. The device of claim 14 further comprising:

a second metal pad electrically coupled to the TSV, wherein the first and the second metal pads are on opposite sides of the substrate; and

a diffusion barrier layer formed of a non-copper-containing material between the second metal pad and the TSV, and spacing the second metal pad and the TSV apart from each other.