Wafer level packaging of micro-electro-mechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) substrates

• US 8,836,116 B2
• Filed: 11/11/2010
• Issued: 09/16/2014
• Est. Priority Date: 10/21/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Hsueh-An
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/944,118
• Publication Number:
  US 20120098122A1
• Time in Patent Office: 1,405 Days
• Field of Search: 257/737, 257/751, 257/E21.087, 257/E23.068, 257/E23.161
• US Class Current: 257/737
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00571 Avoid or control under-cutting
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.

Claims

1. A semiconductor device package, comprising:

a first substrate electrically bonded to a second substrate, wherein the first substrate having a through silicon via extending from a first surface of the first substrate to a first-level metal structure of the first substrate,

wherein the through silicon via is lined with an isolation layer and a conductive layer with a copper-barrier sub-layer and a copper-seed sub-layer, and the through silicon via is partially filled with a copper layer,

wherein the copper layer is deposited on the conductive layer to form a continuous layer and a redistribution layer, the redistribution layer being over and extending laterally along the first surface of the first substrate beyond the through silicon via, and

wherein the through silicon via is electrically connnected to the first-level metal structure through a gate structure and a plurality of contact plugs, and

the through silicon via is electrically connected to a connection structure of the semiconductor device package that enables electrical contact between the semiconductor device package and an external connection structure.

2. The semiconductor device package of claim 1, wherein:

the first substrate includes an integrated circuit device, and

the second substrate includes a micro-electrical-mechanical system (MEMS) device.

3. The semiconductor device package of claim 2, wherein the MEMS device of the second substrate is hermetically sealed by a third substrate and the first substrate;

and wherein the third substrate is bonded to the first substrate.

4. The semiconductor device package of claim 1, wherein the through silicon via physically contacts the gate structure.

5. The semiconductor package of claim 1, wherein the gate structure is polysilicon gate structure.

6. The semiconductor package of claim 1, wherein the copper layer has a thickness in a range from about 5 μ

m to about 10 μ

m.

7. The semiconductor package of claim 1, wherein space in the through silicon via not filled by the copper layer is filled with a polymer layer.

8. The semiconductor package of claim 1, wherein the connection structure is selected from the group consisting of a solder bump and a copper post.

9. The semiconductor package of claim 1, wherein the connection structure physically contacts the redistribution layer.

10. The semiconductor package of claim 1, wherein the copper-barrier sub-layer contains a material selected from a group consisting of Ta, TaN, Ti, TiN, and CoW.

11. The semiconductor package of claim 1, wherein the depth of the through silicon via is in a range from about 100 μ

m to about 200 μ

m.

12. A semiconductor device package, comprising:

a first substrate electrically bonded to a second substrate, wherein the first substrate having a through silicon via extending from a first surface of the first substrate to a polysilicon gate structure of the first; and

an interconnect structure between the polysilicon gate structure and the second substrate,

wherein the polysilicon gate structure is connected to the interconnect structure on an opposite side of the plolysilicon gate structure from the through silicon via, and

wherein the through silicon via is lined with an isolation layer and a conductive layer with a copper-barrier sub-layer and a copper-seed sub-layer,

wherein a copper layer is deposited on the conductive layer,

wherein the through silicone via physically contacts the polysilicon gate structure,and

the through silicon via is electrically coupled to a connection structure of the semiconductor device package that enables electrical contact between the semiconductor device package and an external connection structure.

13. The semiconductor device package of claim 12, wherein:

the first substrate includes an integrated circuit device, and

the second substrate includes a micro-electrical-mechanical system (MEMS) device.

14. The semiconductor device package of claim 13, wherein the MEMS device of the second substrate is hermetically sealed by a third substrate and the first substrate;

and

wherein the third substrate is bonded to the first substrate.

15. A manufacture comprising:

a first substrate comprising;

an electrical device;

an interconnect structure at a first side of the first substrate and over the electrical device, the interconnect structure having a metal structure;

a through-silicon via defined in the first substrate and extending from the interconnect structure to a lower surface of the first substrate, the lower surface being at a second side of the first substrate opposite the first side of the first substrate;

a bump on the lower surface of the first substrate;

a conductive structure in the through-silicon via and electrically connecting the metal structure of the interconnect structure and the bump; and

a polysilicon gate structure between the interconnect structure and the through-silicon via and in contact with the conductive structure;

a second substrate over the interconnect structure of the first substrate, the second substrate comprising;

a micro-electrical-mechanical system (MEMS) device; and

an opening defined in the second substrate; and

a third substrate over the second substrate, the third substrate having a protrusion portion through the opening of the second substrate and in contact with the first substrate,

the first substrate and the third substrate being configured to hermetically seal the MEMS device of the second substrate.

16. The manufacture of claim 15, wherein the first substrate further comprises:

an isolation layer on a side wall of the through-silicon via and between the side wall and the conductive structure.

17. The manufacture of claim 16, wherein the conductive structure is a conductive film lined on the isolation layer.

18. The manufacture of claim 17, wherein the conductive film define a remaining space in the through-silicon via, and the remaining space is filled with a polymer layer.

19. The manufacture of claim 15, wherein the conductive structure is in contact with the metal structure of the interconnect structure.

20. The manufacture of claim 15, wherein the first substrate further comprises:

at least one contact plug connecting thepolysilicon gate structure and the metal structure of the interconnect structure.