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Vertical mount package and wafer level packaging therefor

  • US 8,836,132 B2
  • Filed: 04/03/2012
  • Issued: 09/16/2014
  • Est. Priority Date: 04/03/2012
  • Status: Active Grant
First Claim
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1. A method of manufacturing a chip-scale vertical mount package, the method comprising:

  • providing a device substrate comprising a front surface including a plurality of device regions, and a rear surface opposite the front surface;

    integrally fabricated devices in the device regions on the device substrate;

    sealing the devices in the device regions on the device substrate;

    dicing the device substrate to form a plurality of packages, wherein each package comprises a plurality of side edges between the front and rear surfaces, at least one of the side edges including exposed conductive elements for vertical mount leads, and wherein each of the plurality of packages includes at least one device region.

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