Vertical mount package and wafer level packaging therefor
First Claim
1. A method of manufacturing a chip-scale vertical mount package, the method comprising:
- providing a device substrate comprising a front surface including a plurality of device regions, and a rear surface opposite the front surface;
integrally fabricated devices in the device regions on the device substrate;
sealing the devices in the device regions on the device substrate;
dicing the device substrate to form a plurality of packages, wherein each package comprises a plurality of side edges between the front and rear surfaces, at least one of the side edges including exposed conductive elements for vertical mount leads, and wherein each of the plurality of packages includes at least one device region.
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Accused Products
Abstract
Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.
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Citations
37 Claims
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1. A method of manufacturing a chip-scale vertical mount package, the method comprising:
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providing a device substrate comprising a front surface including a plurality of device regions, and a rear surface opposite the front surface; integrally fabricated devices in the device regions on the device substrate; sealing the devices in the device regions on the device substrate; dicing the device substrate to form a plurality of packages, wherein each package comprises a plurality of side edges between the front and rear surfaces, at least one of the side edges including exposed conductive elements for vertical mount leads, and wherein each of the plurality of packages includes at least one device region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of manufacturing a chip-scale vertical mount package, the method comprising:
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providing a device substrate comprising a plurality of through-substrate contacts extending between front and rear surfaces of the device substrate, the substrate having a plurality of devices integrally fabricated into the front surface of the device substrate and sealed thereon; and dicing the device substrate through at least some of the plurality of through-substrate contacts, each of the severed through-substrate contacts forming a vertical mount lead. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A chip-scale vertical mount package comprising:
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a device substrate comprising a front surface having at least one device integrally fabricated therein, and a rear surface opposite the front surface; a capping substrate comprising a front surface and a rear surface opposite the front surface, the capping substrate disposed over the device substrate such that the rear surface of the capping substrate faces the front surface of the device substrate, wherein the at least one device is sealed within a cavity defined by the device substrate and the capping substrate, a plurality of side edges extending between the front surface of the capping substrate and the rear surface of the device substrate, at least one of the side edges including exposed conductive elements along the device substrate for vertical mount leads. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 35, 36, 37)
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30. A chip-scale vertical mount package comprising:
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a device substrate comprising a front surface and a rear surface opposite the front surface, wherein the device substrate is made of glass or silicon; at least one device integrally fabricated in the front surface of the substrate and sealed thereon; and a plurality of side edges extending between the front and rear surfaces of the device substrate, at least one of the side edges including exposed conductive elements along the device substrate for vertical mount leads. - View Dependent Claims (31, 32, 33, 34)
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Specification