Package-on-package assembly with wire bond vias

• US 8,836,136 B2
• Filed: 02/24/2012
• Issued: 09/16/2014
• Est. Priority Date: 10/17/2011
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Chau, Ellis, Co, Reynaldo, Alatorre, Roseann, Damberg, Philip, Wang, Wei-Shun, Yang, Se Young, Zhao, Zhijun
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): SKYLES, TIFNEY L
• Application Number:
  US13/405,108
• Publication Number:
  US 20130093088A1
• Time in Patent Office: 935 Days
• Field of Search: 257/735, 257/774
• US Class Current: 257/774
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/45664 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48245 : the item being metallic
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48997 : Reinforcing structures
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 : Capillary
• CPC Class Codes: H01L 2224/851 : the connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8518 : Translational movements
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/85951 : Forming additional members, e.g. for reinforcing
• CPC Class Codes: H01L 2224/85986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49517 : Additional leads
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1715 : Shape
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/20756 : larger or equal to 60 microns less than 70 microns
• CPC Class Codes: H01L 2924/20757 : larger or equal to 70 microns less than 80 microns
• CPC Class Codes: H01L 2924/20758 : larger or equal to 80 microns less than 90 microns
• CPC Class Codes: H01L 2924/20759 : larger or equal to 90 microns less than 100 microns
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y10T 29/49149 : by metal fusion bonding
• CPC Class Codes: Y10T 29/49151 : by deforming or shaping

Abstract

A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

Claims

1. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;

wire bonds defining edge surfaces and having bases bonded to respective ones of the conductive elements, the bases including first portions of the edge surfaces that extend along the conductive elements with respective second portions of the edge surfaces being at an angle between 25° and

90°

relative to the first portions, the wire bonds further having ends remote from the substrate and remote from the bases; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends wherein the conductive elements are disposed at positions in a pattern having a first minimum pitch between respective adjacent conductive elements of the plurality of conductive elements, and wherein the unencapsulated portions are disposed in positions in a pattern having a second minimum pitch between respective ends of adjacent wire bonds of the plurality of wire bonds, the second pitch being greater than the first pitch.

2. The microelectronic package as set forth in claim 1, wherein the angle is between 80°

and 90°

.

3. The microelectronic package as set forth in claim 1, wherein each of at least some of the unencapsulated portions of the wire bonds includes a ball-shaped portion, each ball-shaped portion being integral with a cylindrical portion of such wire bond, each ball-shaped portion and each cylindrical portion having at least a core consisting essentially of copper, copper alloy or gold.

4. The microelectronic package as set forth in claim 3, wherein the cylindrical portions integral with the ball-shaped portions project beyond a surface of the encapsulation layer.

5. The microelectronic package as set forth in claim 1, wherein at least some of the wire bonds have a core of a primary metal and a metallic finish including a second metal different from the primary metal overlying the primary metal.

6. The microelectronic package as set forth in claim 5, wherein the primary metal is copper and the metallic finish includes a layer of silver.

7. The microelectronic package as set forth in claim 1, wherein the conductive elements are first conductive elements, the microelectronic package further comprising a plurality of second conductive elements electrically connected to the unencapsulated portions of the wire bonds, wherein the second conductive elements do not contact the first conductive elements.

8. The microelectronic package as set forth in claim 7, wherein the second conductive elements are formed by plating in contact with the unencapsulated portions of the wire bonds after forming the encapsulation layer.

9. The microelectronic package as set forth in claim 1, wherein an end of at least one of the wire bonds is displaced in a direction parallel to the first surface of the substrate from its base by at least a distance equal to one of:

a minimum pitch between the conductive elements, and 100 microns, wherein at least one of the wire bonds includes at least one bend between the base thereof and the unencapsulated portion thereof and, wherein the bend of the at least one wire bond is remote from the base thereof and the unencapsulated portion thereof.

10. The microelectronic package as set forth in claim 9, wherein a radius of the bend is greater than twelve times a diameter of a cylindrical portion of the at least one wire bond.

11. The microelectronic package as set forth in claim 9, wherein the radius of the bend is less than ten times a diameter of a cylindrical portion of the at least one wire bond.

12. The microelectronic package as set forth in claim 9, wherein the unencapsulated portion of the at least one wire bond projects above the encapsulation layer in a direction within 25 degrees of perpendicular relative to the first surface of the substrate.

13. The microelectronic package as set forth in claim 1, wherein the conductive elements are non-solder mask defined.

14. The microelectronic package as set forth in claim 1, further comprising ball bonds joined to and overlying portions of the bases of the wire bonds.

15. The microelectronic package as set forth in claim 1, wherein the at least one microelectronic element includes first and second microelectronic elements overlying the first surface within the first region, wherein at least some of the conductive elements are connected with the first microelectronic element, and wherein at least some conductive elements are connected with the second microelectronic element, and wherein the first microelectronic element and the second microelectronic elements are electrically connected with one another within the microelectronic package.

24. A microelectronic assembly comprising:

a first microelectronic package as set forth in claim 1 and further including a plurality of terminals exposed at the second surface of the substrate, and peripheral edges extending in a direction between the first and second surfaces of the substrate;

a second microelectronic package including a substrate having contacts thereon, a second microelectronic element electrically connected with the contacts, and terminals exposed at a surface of the substrate and electrically connected with the second microelectronic element through the contacts, the terminals of the second microelectronic element facing and being electrically connected with respective unencapsulated portions of the wire bonds;

a circuit panel including a first surface and panel contacts exposed at the surface thereof, the first microelectronic package overlying the circuit panel and having the terminals of the first microelectronic package joined to the panel contacts of the circuit panel; and

a monolithic underfill overlying at least one of the peripheral edges of the first microelectronic package and disposed within spaces surrounding the joints between the terminals of the first microelectronic package and the panel contacts of the circuit panel, and disposed within spaces surrounding the joints between the terminals of the second microelectronic package and the first microelectronic package.

16. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;

wire bonds having bases joined to respective ones of the first conductive elements, and end surfaces remote from the substrate and remote from the bases, each wire bond defining an edge surface extending between the base and the end surface thereof;

a dielectric encapsulation layer extending from at least one of the first or second surfaces and filling spaces between the wire bonds such that the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer,

the encapsulation layer including a major surface and an alignment surface sloped with respect to the major surface, at least one unencapsulated portion of the wire bond being positioned on the major surface and the alignment surface being proximate to the major surface at a location adjacent to the unencapsulated portion such that the alignment surface is configured to guide an electrically conductive protrusion disposed above the alignment surface towards the unencapsulated portion of the wire bond.

17. The microelectronic package as set forth in claim 16, wherein the protrusion includes a bond metal.

18. The microelectronic package as set forth in claim 17, wherein the bond metal includes a solder ball attached to a circuit element.

19. The microelectronic package as set forth in claim 16, wherein the encapsulation layer defines a corner region thereof, the encapsulation layer further including at least one minor surface positioned within the corner region and being positioned farther from the substrate than the major surface, the alignment surface extending between the minor surface and the major surface.

20. The microelectronic package as set forth in claim 16, wherein the major surface is a first major surface that overlies the first region of the substrate, the encapsulation layer further defining a second major surface overlying the second region and being positioned closer to the substrate than the major surface, the alignment surface extending between the first and second major surfaces.

21. A microelectronic assembly, comprising:

a first microelectronic package as set forth in claim 16;

a second microelectronic package defining a front surface having terminals thereon; and

a plurality of conductive protrusions connecting at least some of the unencapsulated portions of the wire bonds with respective ones of the terminals;

wherein at least one of the conductive protrusions is positioned in contact with a portion of the alignment surface.

22. The microelectronic package as set forth in claim 21, wherein the conductive protrusions include solder balls.

23. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;

ball bonds joined to at least some of the conductive elements;

wire bonds defining edge surfaces and having bases bonded to the ball bonds atop the at least some conductive elements, the bases including first portions of the edge surfaces that extend over the conductive elements with respective second portions of the edge surfaces being at an angle between 25° and

90°

relative to the first portions, the wire bonds further having ends remote from the substrate and remote from the bases; and

a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.

25. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;

wire bonds having bases joined to respective ones of the first conductive elements, and end surfaces remote from the substrate and remote from the bases, each wire bond defining an edge surface extending between the base and the end surface thereof;

a dielectric encapsulation layer extending from the first surface and filling spaces between the wire bonds such that the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer defining a first surface portion at a first height above the first surface in an area overlying the first region of the substrate and a second surface portion at a second height above the first surface in an area overlying the second region of the substrate, wherein the second height is less than the first height, and wherein unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

26. The microelectronic package as set forth in claim 25, wherein the microelectronic element defines a front face spaced above the first surface at a third height, and wherein the second height is further less than the third height.

27. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;

wire bonds having ball-bond bases joined to respective ones of the first conductive elements, and end surfaces remote from the substrate and remote from the bases by a distance of less than three times a diameter of the base, each wire bond defining an edge surface extending between the base and the end surface thereof;

a dielectric encapsulation layer extending from the first surface and filling spaces between the wire bonds such that the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

28. The microelectronic package as set forth in claim 27, wherein the ball bond bases include a first ball bond joined to the respective conductive elements and second ball bonds joined to the first ball bonds, the end surfaces extending between the end surfaces and the second ball bonds.

29. A microelectronic package comprising:

a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;

at least one microelectronic element overlying the first surface within the first region;

first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;

wire bonds having bases joined to at least some of the first conductive elements, and end surfaces remote from the substrate and remote from the bases, each wire bond defining an edge surface extending between the base and the end surface thereof, wherein at least two of the wire bonds are joined to an individual first conductive element of the plurality of first conductive elements;

a dielectric encapsulation layer extending from at least one of the first or second surfaces and filling spaces between the wire bonds such that the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.