Method for creating a 3D stacked multichip module

• US 8,836,137 B2
• Filed: 04/19/2012
• Issued: 09/16/2014
• Est. Priority Date: 04/19/2012
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US13/451,411
• Publication Number:
  US 20130277852A1
• Time in Patent Office: 880 Days
• Field of Search: 257/774, 257/E23.04, 257/686, 257/208, 257/689, 438/109
• US Class Current: 257/774
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2^N-1 being less than W and 2^N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2^n-1 landing pads for each mask n=1, 2 . . . N.

Claims

1. A three-dimensional stacked multichip module comprising:

a stack of integrated circuit die including W integrated circuit die, W being an integer greater than 1, each of the W integrated circuit die in the stack comprising a patterned conductor layer over a substrate, the patterned conductor layer comprising an electrical contact region, the electrical contact region comprising electrical conductors, at least one of the electrical conductors comprising a landing pad;

the stack of die comprising a first die at one end of the stack and a second die at the other end of the stack, the substrate of the first die facing the patterned conductor layer of the second die;

the landing pads on each die being aligned with those on the other die in the stack;

W electrical connectors extending from a surface of the stack of die and into the stack of die to electrically contact the landing pads on the W integrated circuit die, to create a three-dimensional stacked multichip module having W die levels, the electrical connectors comprising lengths of substantially homogeneous electrically conductive material which lack physical boundaries between the die levels; and

each of the W electrical connectors being electrically connected to one landing pad of one die level.

2. The module according to claim 1, wherein the electrical connectors directly contact the landing pads.

3. The module according to claim 1, wherein at least some of the die comprise device circuitry at a device circuitry location spaced apart from the electrical contact region.

4. The module according to claim 3, wherein the device circuitry for at least one of the die occupies a first portion of the die and the electrical contact region occupies first and second portions of the die on different sides of the device circuitry.

5. The module according to claim 3, wherein the device circuitry for the one of the die occupies first and second spaced apart portions of the die and the electrical contact region occupies a third portion between the first and second portions.

6. The multi-chip module according to claim 1, further comprising a material layer over the patterned conductor layer of the first die.

7. The module according to claim 1, wherein the electrical connectors pass through vertical vias in the electrical contact regions.

8. The module according to claim 1, wherein the landing pads electrically contacted by the electrical connectors are arranged in a stair stepped arrangement.

9. A three-dimensional stacked multi-wafer module comprising:

a stack of integrated circuit wafers;

each integrated circuit wafer comprising a grid of die regions;

at least some of the die regions for each integrated circuit wafer being aligned with die regions of the other integrated circuit wafers of the stack of integrated circuit wafers; and

each die region comprising a three-dimensional stacked multichip module according to claim 1.

10. A three-dimensional stacked multichip module comprising:

a stack of integrated circuit die including W integrated circuit die, W being an integer greater than 1, each of the W integrated circuit die in the stack comprising a patterned conductor layer over a substrate, the patterned conductor layer comprising an electrical contact region, the electrical contact region comprising electrical conductors, at least one of the electrical conductors for a plurality of the die comprising a landing pad;

at least some of the die comprise device circuitry at a device circuitry location spaced apart from the electrical contact region;

the stack of die comprising a first die at one end of the stack and a second die at the other end of the stack, the substrate of the first die facing the patterned conductor layer of the second die;

a material layer over the patterned conductor layer of the first die;

the landing pads on the die in the stack of the die being aligned;

W electrical connectors passing through vertical vias in the electrical contact regions to extend from a surface of the stack of die and into the stack of die to electrically contact selected ones of the landing pads on the W integrated circuit die, the selected ones of the landing pads arranged in a stair stepped arrangement, to create a three-dimensional stacked multichip module having W die levels; and

each of the W electrical connectors being electrically connected to one landing pad of one die level.

11. A three-dimensional stacked multi-wafer module comprising:

a stack of integrated circuit wafers;

each integrated circuit wafer comprising a grid of die regions;

at least some of the die regions for each integrated circuit wafer being aligned with die regions of the other integrated circuit wafers of the stack of integrated circuit wafers; and

each of a plurality of said at least some of the die regions comprising a three-dimensional stacked multichip module according to claim 10.

12. A three-dimensional stacked multichip module comprising:

a stack of dies, each die in the stack comprising an electrical contact region over a substrate, the electrical contact region comprising a plurality of pads;

the stack of dies comprising a first die at one end of the stack and a second die at the other end of the stack, the substrate of the first die facing the plurality of pads of the second die;

the plurality of pads on each die being aligned with those on the other die in the stack; and

a substantially homogeneous electrically conductive material which lacks physical boundaries between the dies in the stack of dies and is connected to at least some of the pads in the plurality of pads on the first die through vias in corresponding pads in the plurality of pads on the second die.