Voltage level shifter

• US 8,836,406 B2
• Filed: 02/09/2014
• Issued: 09/16/2014
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Wang, Meng
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US14/176,136
• Publication Number:
  US 20140152352A1
• Time in Patent Office: 219 Days
• Field of Search: None
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power

Abstract

A level shifter includes a latch supplied at a first voltage V_DD1. First and second switches are connected in series with first and second latches and are cross-coupled to maintain the state of the latches during a stability period. A controller responds to a change of state of an input signal at a voltage different from the first voltage at an end of the stability period to deactivate both the first and second switches, to cause third and fourth switches to deactivate both the first and second latches during a transition period, and subsequently to change the state of the latch and maintain the changed state during the subsequent stability period. This avoids undesirable compromise between current consumption and transfer delay, as in a conventional level shifter.

Claims

1. A level shifter, comprising:

a latch supplied at a first voltage and having first and second latch elements one of which is activated and the other deactivated in respective states of said latch;

first and second switch elements connected in series with said first and second latch elements and coupled to maintain the state of said second and first latch elements respectively during a stability period;

an output connected to at least one of said first and second latch elements;

third and fourth switch elements connected to control said first and second latch elements respectively during a transition period, wherein said first and second latch elements have respective first and second current conduction paths in series with said first and second switch elements and first and second control electrodes connected with said second and first switch elements and with said third and fourth switch elements, wherein said first voltage is supplied between first and second voltage supply nodes, and said third and fourth switch elements include respective third and fourth control elements having control electrodes and current conduction paths connected between said first and second control electrodes and said first voltage supply node, and third and fourth drive elements having current conduction paths connected between said control electrodes of said third and fourth control elements and said second voltage supply node; and

a controller for responding to a change of state of an input signal at a voltage different from said first voltage at an end of said stability period to deactivate both said first and second switch elements, to cause said third and fourth switch elements to deactivate both said first and second latch elements during said transition period, and subsequently to activate one of said first and second switch elements and the corresponding one of said second and first latch elements to change the state of said latch and maintain the changed state during the subsequent stability period.

2. The level shifter of claim 1, further comprising first and second biased elements connected in series between said first and second switch elements and said first and second latch elements respectively, said first and second biased elements being biased by a second voltage that is less than said first voltage.

3. The level shifter of claim 1, wherein said controller comprises a capacitive timing element that defines a duration of said transition period.

4. The level shifter of claim 3, wherein said capacitive timing element defines a delayed signal triggered by said change of state of said input signal and defines said duration of said transition period relative to a conjunction between assertion/de-assertion of said input signal and de-assertion/assertion of said delayed signal.

5. The level shifter of claim 1, wherein said controller comprises a gate element defining a start of said stability period as a function of an end of said transition period.

6. The level shifter of claim 5, wherein said gate element defines an end of said stability period as a function of said change of state of said input signal.

7. The level shifter of claim 1, wherein said third and fourth switch elements include respective resistive elements connected between said control electrodes of said third and fourth control elements and said first voltage supply node in series with said current conduction paths of said third and fourth drive elements.

8. A gate driver, comprising:

a charge pump;

a power transistor having a gate electrode; and

a level shifter, including,

a latch supplied at a first voltage and having first and second latch elements one of which is activated and the other deactivated in respective states of said latch,

first and second switch elements connected in series with said first and second latch elements and coupled to maintain the state of said second and first latch elements respectively during a stability period;

an output connected to at least one of said first and second latch elements,

third and fourth switch elements connected to control said first and second latch elements respectively during a transition period, and

a controller for responding to a change of state of an input signal at a voltage different from said first voltage at an end of said stability period to deactivate both said first and second switch elements, to cause said third and fourth switch elements to deactivate both said first and second latch elements during said transition period, and subsequently to activate one of said first and second switch elements and the corresponding one of said second and first latch elements to change the state of said latch and maintain the changed state during the subsequent stability period,

wherein said charge pump supplies power to said level shifter, and said output of said level shifter applies a voltage to said gate electrode of said power transistor.