Digital to-analog conversion circuit

• US 8,836,561 B2
• Filed: 09/12/2013
• Issued: 09/16/2014
• Est. Priority Date: 10/12/2012
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kanagawa, Norifumi, Shimizu, Yasuhide
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US14/025,254
• Publication Number:
  US 20140104087A1
• Time in Patent Office: 369 Days
• Field of Search: 341134-136, 341/144, 341/153
• US Class Current: 341/144
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

A D/A conversion circuit includes: current generation circuits each including a constant current source configured to generate a current, a first MOSFET connected to the constant current source and configured to control a supply destination of the current, a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET, and a first discharge switch connected to the first gate control section and the gate of the first MOSFET, controlled to be turned on at the same time as the first gate control section supplies the second voltage and controlled to be turned off before the first gate control section supplies the first voltage; a first current addition line; a discharge line; a first resistor connected to the first current addition line; and a voltage source configured to supply the second voltage to the first gate control sections.

Claims

1. A digital-to-analog conversion circuit, comprising:

a plurality of current generation circuits each including

a constant current source configured to generate a current corresponding to a predetermined parameter,

a first metal-oxide semiconductor field-effect transistor (MOSFET) that is connected to the constant current source and is configured to control a supply destination of the current,

a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET to control the first MOSFET, the first MOSFET being controlled to be turned off by the first voltage and turned on by the second voltage, and

a first discharge switch that is connected to the first gate control section and the gate of the first MOSFET, is controlled to be turned on at the same time as the first gate control section supplies the second voltage to discharge charge accumulated in a parasitic capacitance to a predetermined target, the parasitic capacitance being in the first gate control section and the gate of the first MOSFET, and is controlled to be turned off before the first gate control section supplies the first voltage;

a first current addition line, to which the first MOSFETs are connected in parallel;

a discharge line configured to discharge the charge;

a first resistor connected to the first current addition line at a predetermined potential; and

a voltage source configured to supply the second voltage to the first gate control sections.

2. The digital-to-analog conversion circuit according to claim 1,

wherein the plurality of current generation circuits each include

a second MOSFET that is connected to the constant current source and is configured to exclusively control the supply destination of the current for the first MOSFET,

a second gate control section configured to exclusively supply the first voltage and the second voltage to control the second MOSFET, the second MOSFET being controlled to be turned off by the first voltage and turned on by the second voltage, and

a second discharge switch that is connected to the second gate control section and a gate of the second MOSFET, is controlled to be turned on at the same time as the second gate control section supplies the second voltage to discharge charge accumulated in a parasitic capacitance to the discharge line, the parasitic capacitance being in the second gate control section and the gate of the second MOSFET, and is controlled to be turned off before the second gate control section supplies the first voltage,

the digital-to-analog conversion circuit further comprising:

a second current addition line, to which the second MOSFETs are connected in parallel; and

a second resistor connected to the second current addition line at a predetermined potential,

wherein the voltage source is configured to supply the second voltage to the second gate control sections.

3. The digital-to-analog conversion circuit according to claim 2, wherein

at least one of the first current addition line and the second current addition line is used as an digital-to-analog conversion output, and

the voltage source has an impedance higher than that of the first discharge switch.

4. The digital-to-analog conversion circuit according to claim 3, wherein

each of the first MOSFET and the second MOSFET includes a P-channel MOSFET,

the first voltage includes a positive power-supply voltage,

the second voltage includes a voltage higher than a ground potential, and

the discharge line includes ground.

5. The digital-to-analog conversion circuit according to claim 3, wherein

each of the first MOSFET and the second MOSFET includes an N-channel MOSFET,

the first voltage includes a ground potential,

the second voltage includes a voltage lower than a positive power-supply voltage, and

the discharge line includes a positive supply terminal.