High resolution capacitance to code converter

• US 8,836,669 B1
• Filed: 12/04/2013
• Issued: 09/16/2014
• Est. Priority Date: 09/13/2013
• Status: Active Grant

• Current Assignee: Parade Technologies, Ltd.
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ogirko, Roman, Klein, Hans, Maharyta, Andriy
• Primary Examiner(s): Chang, Kent
• Assistant Examiner(s): ROSARIO, NELSON M
• Application Number:
  US14/097,138
• Time in Patent Office: 286 Days
• Field of Search: 345/173, 345/174, 345/156, 345/179, 178/18.06, 178/19.03, 324/658, 324/683, 324/684, 324/676, 324/649, 324/600, 324/686, 324/665, 324/672, 324/679, 324/519, 324/548, 324/76.66, 324/76.11, 326/38, 326/41, 326/47, 710/18, 710/266
• US Class Current: 345/174
• CPC Class Codes: G06F 3/04162 for exchanging data with external devices, e.g. smart pens, via the digitiser sensing hardware
• CPC Class Codes: G06F 3/0442 using active external devices, e.g. active pens, for transmitting changes in electrical potential to be received by the digitiser
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

An integration circuit including a first capacitor is operatively coupled to a comparator. The comparator is configured to compare a first capacitor voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison. A current generator is operatively coupled with the integration circuit and configured to balance charge on the first capacitor. A control unit is operatively coupled to the comparator and the current generator and configured to balance charge on the first capacitor by sensing the first comparator output and controlling the current generator based on the first comparator output.

Claims

1. An apparatus comprising:

an integration circuit comprising a first capacitor and a second capacitor, the integration circuit coupled to a capacitive sense array;

a comparator, operatively coupled to the integration circuit, to compare a first capacitor voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison;

a current generator, operatively coupled with the integration circuit, the current generator configured to balance charge on the first capacitor, the second capacitor configured to integrate charge when the current generator balances charge on the first capacitor, and be charge balanced by the current generator when the first capacitor integrates charge; and

a control unit, operatively coupled to the comparator and the current generator, the control unit configured to balance charge on the first capacitor by sensing the first comparator output and controlling the current generator based on the first comparator output.

2. The apparatus of claim 1, further comprising:

an attenuator circuit, operatively coupled to the integration circuit, the attenuator circuit to sink or source charge to the integration circuit and the integrator circuit to integrate the charge.

3. The apparatus of claim 2, wherein the attenuator circuit comprises a programmable current-mode attenuator circuit.

4. The apparatus of claim 1, wherein the control unit is configured to measure a charge balancing period, the charge balancing period beginning at a first state when the control unit senses from the first comparator output a difference between the first capacitor voltage and the reference voltage and ends at a second state when the control unit senses from the first comparator output the first capacitor voltage and the reference voltage are balanced and the control unit latches the second state using a clock signal.

5. The apparatus of claim 4, wherein the control unit is configured to generate a quantization error during the charge balancing period, wherein the quantization error is accumulated on the first capacitor over successive charge balancing periods.

6. The apparatus of claim 4, further comprising:

a counter, coupled to the control unit, to convert the charge balancing period into a digital output code.

7. The apparatus of claim 1, wherein the current generator performs one of at least sinking or sourcing charge to the integration circuit.

8. The apparatus of claim 1, wherein the first capacitor comprises a nonlinear capacitor.

9. A method comprising:

integrating charge on a first capacitor, the first capacitor coupled to a capacitive sense array;

comparing a first capacitor voltage on the first capacitor to a reference voltage at a comparator, the comparator to produce a first comparator output based on a first comparison;

balancing, by a current generator, charge on the first capacitor based on the first comparator output of the first comparison;

measuring a charge balancing period, based on the charge balancing, by the current generator, on the first capacitor; and

accumulating a quantization error over successive charge balancing periods.

10. The method of claim 9, further comprising:

attenuating an input charge at an attenuator circuit to produce an attenuated output charge at an attenuator output; and

supplying the attenuated output charge to the first capacitor.

11. The method of claim 10, wherein the attenuator circuit comprises a programmable current-mode attenuator circuit.

12. The method of claim 9, further comprising:

controlling, by a control unit, the charge balancing on the first capacitor by the current generator based on the first comparator output.

13. The method of claim 9, further comprising:

alternately integrating charge on one of the first capacitor or a second capacitor while balancing charge on an other of the first capacitor or second capacitor;

comparing a second capacitor voltage of the second capacitor to the reference voltage at the comparator to produce a second comparator output based on a second comparison; and

measuring the charge balancing period based on the charge balancing by the current generator on the second capacitor.

14. The method of claim 9, further comprising:

converting the charge balancing period into a digital output code.

15. The method of claim 9, wherein the first capacitor comprises a nonlinear capacitor.

16. A system comprising:

a capacitance-sensing circuit configured to measure touch data from a capacitive sense array, the capacitance-sensing circuit comprising;

a first capacitor configured to alternately integrate charge or balance charge;

a second capacitor configured to alternately integrate charge or balance charge;

a comparator, operatively coupled to the first capacitor to compare a first capacitor voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison;

a current generator, operatively coupled with the first capacitor, the current generator configured to balance charge on the first capacitor, the second capacitor configured to integrate charge when the current generator balances charge on the first capacitor, and the current generator configured to balance charge on the second capacitor when the first capacitor integrates charge; and

a control unit, operatively coupled to the comparator and the current generator, the control unit configured to balance charge on the first capacitor by sensing the first comparator output and controlling the current generator based on the first comparator output.

17. The system of claim 16, wherein the control unit is configured to measure a charge balancing period, the charge balancing period beginning at a first state when the control unit senses from the first comparator output, a difference between the first capacitor voltage and the reference voltage and ends at a second state when the control unit senses from the first comparator output, the first capacitor voltage and the reference voltage are balanced and the control unit latches the second state by a clock signal.

18. The system of claim 17, wherein the capacitance-sensing circuit is further configured to convert the charge balancing period to a digital output code.