Solid-state imaging apparatus having pixels with plural semiconductor regions

• US 8,836,833 B2
• Filed: 06/14/2011
• Issued: 09/16/2014
• Est. Priority Date: 07/07/2010
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Yamashita, Yuichiro, Yamazaki, Yasuo, Fujimura, Masaru, Kikuchi, Shin, Kono, Shoji, Shimizu, Shinichiro, Arishima, Yu
• Primary Examiner(s): CHEN, CHIA WEI A
• Application Number:
  US13/159,510
• Publication Number:
  US 20120008031A1
• Time in Patent Office: 1,190 Days
• Field of Search: 348294-310
• US Class Current: 348/301
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14663 Indirect radiation imagers, e.g. using luminescent members
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 5/32 Transforming X-rays cameras or camera modules for generating image signals from X-rays H04N23/30; circuitry of SSIS for transforming X-rays into image signals H04N25/30

Abstract

A solid-state imaging apparatus has a pixel array in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns, and a plurality of column signal lines are arranged, wherein each of the plurality of pixels includes a photoelectric converter including a first well formed in a semiconductor substrate and having a first conductivity type, and an impurity region arranged in the first well and having a second conductivity type different from the first conductivity type, and an in-pixel readout circuit which outputs, to the column signal line, a signal corresponding to charges generated in the photoelectric converter, the in-pixel readout circuit including a circuit element arranged in a second well having the first conductivity type, and wherein the first well and the second well are isolated by a semiconductor region having the second conductivity type.

Claims

1. A solid-state imaging apparatus having a pixel array in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns, and a plurality of column signal lines are arranged,

each of the plurality of pixels comprising:

a first semiconductor region having a first conductivity type;

a photoelectric converter including a second semiconductor region arranged in the first semiconductor region and having a second conductivity type that is different from the first conductivity type, and a third semiconductor region arranged in the second semiconductor region and having the first conductivity type;

a charge-voltage converter configured to convert charges stored in the photoelectric converter to a voltage;

a reset transistor configured to reset the charge-voltage converter;

a first amplifier circuit configured to output a signal corresponding to a potential of the charge-voltage converter; and

a clamp capacitance connected to an output node of the first amplifier circuit,

wherein the clamp capacitance is arranged on a fourth semiconductor region that is arranged in the first semiconductor region and having the second conductivity type, and

wherein the second semiconductor region and the fourth semiconductor region are isolated by the first semiconductor region.

2. The apparatus according to claim 1, wherein the clamp capacitance comprises a first electrode formed in the fourth semiconductor region, and a second electrode formed on an insulating film on the first electrode.

3. The apparatus according to claim 2, wherein the first electrode includes a sixth semiconductor region formed in the fourth semiconductor region.

4. The apparatus according to claim 1, wherein a maximum depth of the second semiconductor region is larger than a maximum depth of the fourth semiconductor region.

5. The apparatus according to claim 1, wherein the second semiconductor region comprises a stacked structure portion formed by stacking a plurality of semiconductor regions having the first conductivity type.

6. The apparatus according to claim 5, wherein each of the plurality of pixels further comprises a semiconductor region having the second conductivity type, which is arranged to surround a periphery of the stacked structure portion and which has a maximum depth smaller than a maximum depth of the stacked structure portion.

7. An imaging system comprising:

a solid-state imaging apparatus defined in claim 1; and

a processor which processes a signal output from the solid-state imaging apparatus.

8. The apparatus according to claim 1, wherein each of the plurality of pixels further comprises a fifth semiconductor region arranged between the second semiconductor region and the fourth semiconductor region and having the first conductivity type.