Circuit for generating write signal, variable resistance memory device, and method for programming variable resistance memory

• US 8,837,197 B2
• Filed: 02/09/2012
• Issued: 09/16/2014
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Young-Don, Oh, Young-Hoon, Song, Ick-Hyun
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US13/369,361
• Publication Number:
  US 20130051120A1
• Time in Patent Office: 950 Days
• Field of Search: 365/148, 365/163, 365/191, 365/210.11
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse

Abstract

A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.

Claims

1. A circuit for generating a write signal, the circuit comprising:

a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell; and

a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell, generates a write signal by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and outputs the write signal to the to-be-programmed memory cell;

wherein the pre-emphasis signal generator comprises a signal magnitude reducing unit that reduces a magnitude of the program signal when the program signal is combined with the pre-emphasis signal.

2. The circuit of claim 1, wherein the pre-emphasis signal generator increases a magnitude of the pre-emphasis signal with an increase in distance between the to-be-programmed memory cell and the write driver.

3. The circuit of claim 1, wherein the pre-emphasis signal generator increases a pulse-width of the pre-emphasis signal with an increase in distance between the to-be-programmed memory cell and the write driver.

4. The circuit of claim 1, wherein the pre-emphasis signal generator comprises:

a signal width adjusting unit that adjusts a pulse width of the pre-emphasis signal according to the time in which a control signal is applied; and

a signal magnitude adjusting unit that adjusts a magnitude of the pre-emphasis signal according to the magnitude of a bias signal.

5. The circuit of claim 4, wherein the write driver comprises a feedback amplifier that generates the write signal.

6. The circuit of claim 1, wherein the pre-emphasis signal generator generates a multi-bit digital control signal according to the location information of the to-be-programmed memory cell, and adjusts a magnitude of the pre-emphasis signal according to the generated digital control signal.

7. The circuit of claim 6, wherein the pre-emphasis signal generator adjusts the magnitude of the pre-emphasis signal in accordance with a linear decoding scheme.

8. The circuit of claim 6, wherein the pre-emphasis signal generator adjusts the magnitude of the pre-emphasis signal in accordance with a binary decoding scheme.

9. The circuit of claim 6, wherein the pre-emphasis signal generator comprises a plurality of pre-emphasis signal magnitude adjusting transistors having respectively different channel widths.

10. The circuit of claim 1, wherein the signal magnitude reducing unit comprises a ground transistor that is responsive to a negative control signal to divert at least some of the program signal to a ground terminal.

11. The circuit of claim 1, wherein a first portion of the write signal has a larger magnitude than the program signal, and a second portion of the write signal has a smaller magnitude than the program signal.

12. The circuit of claim 1, wherein the program signal, the pre-emphasis signal and the write signal are respective current signals.

13. A variable resistance memory device comprising:

a memory cell array including a plurality of variable resistance memory cells;

an address decoder that receives address information and outputs location information of a to-be-programmed memory cell among the plurality of variable resistance memory cells;

a pre-emphasis signal generator that receives the location information of the to-be-programmed memory cell from the address decoder and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell; and

a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell, generates a write signal by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and outputs the write signal to the to-be-programmed memory cell;

wherein the pre-emphasis signal generator comprises a signal magnitude reducing unit that reduces a magnitude of the program signal when the program signal is combined with the pre-emphasis signal.

14. The variable resistance memory of claim 13, wherein the variable resistance memory cell includes a phase change memory cell.

15. A method of programming a memory device including a write driver operatively connected to a memory cell array, the memory cell array including a plurality of variable resistance memory cells, the method comprising:

generating a write signal in accordance with a write data to be programmed in a to-be-programmed variable resistance memory cell of the memory cell array;

generating a pre-emphasis signal in accordance with a relative location of the to-be-programmed variable resistance memory cell within the memory cell array;

combining the write signal and the pre-emphasis signal to generate a program signal;

applying the program signal to the to-be-programmed variable resistance memory cell; and

combining the program signal with the pre-emphasis signal in conjunction with reducing a magnitude of the program signal.

16. The method of claim 15, wherein the pre-emphasis signal is generated such that a magnitude of the program signal increases with an increase in distance between the to-be-programmed variable resistance memory cell and the write driver.

17. The method of claim 16, wherein the variable resistance memory cells are phase-change memory cells, and the program signal is one of a SET write current and a RESET write current.

18. The method of claim 16, wherein the program signal is applied to a bit line of the memory cell array.

19. The method of claim 15, further comprising decoding an address of the to-be-programmed variable resistance memory cell to determine the relative location of the to-be-programmed variable resistance memory cell within the memory cell array.