Semiconductor device

• US 8,837,203 B2
• Filed: 05/09/2012
• Issued: 09/16/2014
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Shionoiri, Yutaka, Kobayashi, Hidetomo
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/467,490
• Publication Number:
  US 20120292613A1
• Time in Patent Office: 860 Days
• Field of Search: 365/129, 365/149, 365/154, 365/174
• US Class Current: 365/149
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.

Claims

1. A semiconductor device comprising a memory cell including:

a memory;

a first transistor including an oxide semiconductor layer;

a first capacitor; and

a switch,

wherein an output port of the memory is electrically connected to one terminal of the switch,

wherein the other terminal of the switch is electrically connected to one of a source and a drain of the first transistor, and

wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor.

2. The semiconductor device according to claim 1, wherein the memory is a volatile memory.

3. The semiconductor device according to claim 1,

wherein the memory comprises a second capacitor and a second transistor, and

wherein the second transistor includes a semiconductor including silicon.

4. The semiconductor device according to claim 1, wherein the switch is a data collision prevention switch.

5. The semiconductor device according to claim 1,

wherein the switch includes an oxide semiconductor layer, and

wherein the oxide semiconductor layer in the first transistor and the oxide semiconductor layer in the switch are formed of a common layer.

6. The semiconductor device according to claim 1, further comprising a pipeline circuit,

wherein the pipeline circuit comprises a first stage and a second stage, and

wherein the memory cell is provided between the first stage and the second stage.

13. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least one of indium and zinc in a channel formation region.

7. A semiconductor device comprising a memory cell including:

a memory;

a first transistor including an oxide semiconductor layer;

a first capacitor;

a second transistor; and

a delay circuit,

wherein an output port of the memory is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor,

wherein an input terminal of the delay circuit is electrically connected to a gate of the first transistor, and

wherein an output terminal of the delay circuit is electrically connected to a gate of the second transistor.

8. The semiconductor device according to claim 7, wherein the memory is a volatile memory.

9. The semiconductor device according to claim 7,

wherein the memory comprises a second capacitor and a third transistor, and

wherein the third transistor includes a semiconductor including silicon.

10. The semiconductor device according to claim 7, wherein the second transistor is a data collision prevention switch.

11. The semiconductor device according to claim 7,

wherein the second transistor includes an oxide semiconductor layer, and

wherein the oxide semiconductor layer in the first transistor and the oxide semiconductor layer in the second transistor are formed of a common layer.

12. The semiconductor device according to claim 7, further comprising a pipeline circuit,

wherein the pipeline circuit comprises a first stage and a second stage, and

wherein the memory cell is provided between the first stage and the second stage.

14. The semiconductor device according to claim 7, wherein the oxide semiconductor layer includes at least one of indium and zinc in a channel formation region.