Electronic devices including two or more substrates electrically connected together and methods of forming such electronic devices

• US 8,837,212 B2
• Filed: 09/26/2013
• Issued: 09/16/2014
• Est. Priority Date: 03/10/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Meade, Roy E., Sandhu, Gurtej S.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/038,472
• Publication Number:
  US 20140029225A1
• Time in Patent Office: 355 Days
• Field of Search: 365/171, 365/230.06, 365/173
• US Class Current: 365/171
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 19/0808 using magnetic domain propagation
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/09381 : Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/36 : Assembling printed circuits with other printed circuits H05K7/142 takes precedence
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence
• CPC Class Codes: H05K 7/04 : on conductive chassis
• CPC Class Codes: Y10S 977/932 : for electronic or optoelectronic application
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base

Abstract

Electronic devices may include a first substrate bearing circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. A second substrate may be electrically connected to at least one of the microscale bond pads. Methods of forming electronic devices may include positioning a first substrate adjacent to a second substrate. The first substrate may bear circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. The second substrate may be electrically connected to at least one of the microscale bond pads.

Claims

1. An electronic device, comprising:

a first substrate bearing circuitry components at a nanoscale pitch within the first substrate, the first substrate comprising;

microscale bond pads on a surface of the first substrate; and

a via electrically connecting one of the microscale bond pads to one of the circuitry components; and

a second substrate electrically connected to at least one of the microscale bond pads.

2. The electronic device of claim 1, wherein each microscale bond pad is located over at least two circuitry components.

3. The electronic device of claim 1, wherein the via is offset from a geometrical center of the one of the microscale bond pads.

4. The electronic device of claim 1, wherein the via is aligned with a geometrical center of the one of the microscale bond pads.

5. The electronic device of claim 1, further comprising additional vias electrically connecting additional bond pads of the microscale bond pads to additional components of the circuitry components.

6. The electronic device of claim 1, wherein at least some of the nanoscale pitch components are conductive traces extending at least substantially parallel to each other through a portion of the first substrate.

7. The electronic device of claim 6, wherein the conductive traces are magnetic shift registers including a plurality of domains and the vias are a plurality of magnetic tunneling junctions.

8. The electronic device of claim 6, wherein at least some of the circuitry components are memory cells and at least another of the circuitry components is a charge pump, a decode-and-addressing circuit, a sense amplifier, or an I/O circuit.

9. The electronic device of claim 1, wherein an area of each of the microscale bond pads is 2,000 μ

m² or greater.

10. The electronic device of claim 1, wherein the nanoscale pitch at which the circuitry components are positioned is 100 nm or less.

11. The electronic device of claim 1, wherein each of the microscale bond pads exhibits a shape selected from the group consisting of square, rectangular, hexagonal, and triangular.

12. The electronic device of claim 11, wherein the microscale bond pads collectively form a bond raster pattern or a bond shift pattern.

13. A method of forming an electronic device, comprising:

positioning a first substrate adjacent to a second substrate, the first substrate bearing circuitry components at a nanoscale pitch within the first substrate, the first substrate comprising;

microscale bond pads on a surface of the first substrate; and

a via electrically connecting one of the microscale bond pads to one of the circuitry components; and

electrically connecting the second substrate to at least one of the microscale bond pads.

14. The method of claim 13, further comprising forming the circuitry components of the first substrate at the nanoscale pitch at a first temperature and forming circuitry within the second substrate at a second, higher temperature.

15. The method of claim 14, wherein forming the circuitry components at the first temperature comprises forming the circuitry components at a temperature below 450°

C.

16. The method of claim 14, wherein forming the circuitry within the second substrate at the second, higher temperature comprises forming the circuitry within the second substrate at a temperature below about 1,100°

C.

17. The method of claim 13, further comprising forming the circuitry components of the first substrate at a nanoscale pitch of 100 nm or less.

18. The method of claim 13, further comprising forming a surface of each bond pad of the microscale bond pads to exhibit an area of 2,000 μ

m² or greater.

19. The method of claim 13, further comprising forming the microscale bond pads on the surface of the first substrate in one of a bond raster pattern and a bond shift pattern.

20. The method of claim 13, further comprising forming the one of the microscale bond pads at a position offsetting a geometrical center of the one of the microscale bond pads from the via.