Semiconductor device

• US 8,837,232 B2
• Filed: 07/12/2013
• Issued: 09/16/2014
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nagatsuka, Shuhei, Matsuzaki, Takanori, Inoue, Hiroki, Kato, Kiyoshi
• Primary Examiner(s): NGUYEN, HIEN N
• Application Number:
  US13/940,493
• Publication Number:
  US 20130301367A1
• Time in Patent Office: 431 Days
• Field of Search: 365/154, 365/189.05, 365/189.09, 365/189.15, 365/189.16
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in off-state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.

Claims

1. A semiconductor device comprising:

a memory cell array comprising m×

n memory cells;

a driver circuit; and

a potential generating circuit,

wherein the driver circuit comprises a K-bit latch portion and a writing circuit including a K-bit multiplexer in every column of the memory cells, and

wherein the writing circuit is connected to the potential generating circuit and the K-bit latch portion.

2. The semiconductor device according to claim 1,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the first transistor is a p-channel transistor and the second transistor is an re-channel transistor.

3. The semiconductor device according to claim 1,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

4. A semiconductor device comprising:

a memory cell array comprising m×

n memory cells;

a first driver circuit;

a second driver circuit;

a potential generating circuit;

a bit line;

a source line; and

a gate line,

wherein the first driver circuit comprises a K-bit latch portion and a writing circuit including a K-bit multiplexer in every column of the memory cells, and

wherein the writing circuit is connected to the potential generating circuit and the K-bit latch portion.

5. The semiconductor device according to claim 4,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the source line is connected to the first source electrode,

wherein the bit line is connected to the first drain electrode and the second drain electrode,

wherein the gate line is connected to the second gate electrode, and

wherein the first gate electrode is connected to the second source electrode.

6. The semiconductor device according to claim 4,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the first transistor is a p-channel transistor and the second transistor is an re-channel transistor.

7. The semiconductor device according to claim 4,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

8. The semiconductor device according to claim 4, wherein a plurality of memory cells including the one of the memory cells is connected in parallel between the bit line and the source line.

9. The semiconductor device according to claim 4, wherein a plurality of memory cells including the one of the memory cells is connected in series between the bit line and the source line.

10. The semiconductor device according to claim 4, wherein the potential generating circuit is connected to the first driver circuit and the second driver circuit.

11. A semiconductor device comprising:

a memory cell array comprising m×

n memory cells;

a first driver circuit;

a second driver circuit;

a K-bit counter (K is a natural number);

a potential generating circuit;

a bit line;

a source line; and

a gate line,

wherein the first driver circuit comprises a K-bit latch portion and a reading circuit in every column of the memory cells,

wherein the K-bit counter is connected to the reading circuit, and

wherein the reading circuit is connected to the K-bit latch portion.

12. The semiconductor device according to claim 11,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the source line is connected to the first source electrode,

wherein the bit line is connected to the first drain electrode and the second drain electrode,

wherein the gate line is connected to the second gate electrode, and

wherein the first gate electrode is connected to the second source electrode.

13. The semiconductor device according to claim 11,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the first transistor is a p-channel transistor and the second transistor is an re-channel transistor.

14. The semiconductor device according to claim 11,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

15. The semiconductor device according to claim 11, wherein a plurality of memory cells including the one of the memory cells is connected in parallel between the bit line and the source line.

16. The semiconductor device according to claim 11, wherein a plurality of memory cells including the one of the memory cells is connected in series between the bit line and the source line.

17. The semiconductor device according to claim 11,

wherein the reading circuit comprises a load, a sense amplifier, and a NAND circuit,

wherein the sense amplifier is connected to one of inputs of the NAND circuit,

wherein a memory reading line is connected to the other of the inputs of the NAND circuit, and

wherein the K-bit latch portion is connected to an output of the NAND circuit.

18. The semiconductor device according to claim 11, wherein the potential generating circuit is connected to the first driver circuit and the second driver circuit.

19. The semiconductor device according to claim 11, wherein the K-bit counter is electrically connected to an input of the K-bit latch portion.

20. A semiconductor device comprising:

a memory cell array comprising m×

n memory cells;

a first driver circuit;

a second driver circuit;

a K-bit counter (K is a natural number);

a potential generating circuit;

a bit line;

a source line; and

a gate line,

wherein the first driver circuit comprises a K-bit latch portion, a writing circuit including a K-bit multiplexer, and a reading circuit in every column of the memory cells,

wherein the K-bit counter is connected to the reading circuit, and

wherein the K-bit latch portion is connected to the writing circuit and the reading circuit.

21. The semiconductor device according to claim 20,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the source line is connected to the first source electrode,

wherein the bit line is connected to the first drain electrode and the second drain electrode,

wherein the gate line is connected to the second gate electrode, and

wherein the first gate electrode is connected to the second source electrode.

22. The semiconductor device according to claim 20,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the first transistor is a p-channel transistor and the second transistor is an re-channel transistor.

23. The semiconductor device according to claim 20,

wherein one of the memory cells comprises:

a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and

a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,

wherein the second channel formation region of the second transistor comprises an oxide semiconductor.

24. The semiconductor device according to claim 20, wherein a plurality of memory cells including the one of the memory cells is connected in parallel between the bit line and the source line.

25. The semiconductor device according to claim 20, wherein a plurality of memory cells including the one of the memory cells is connected in series between the bit line and the source line.

26. The semiconductor device according to claim 20,

wherein the reading circuit comprises a load, a sense amplifier, and a NAND circuit,

wherein the sense amplifier is connected to one of inputs of the NAND circuit,

wherein a memory reading line is connected to the other of the inputs of the NAND circuit, and

wherein the K-bit latch portion is connected to an output of the NAND circuit.

27. The semiconductor device according to claim 20, wherein the potential generating circuit is connected to the first driver circuit and the second driver circuit.

28. The semiconductor device according to claim 20, wherein the K-bit counter is electrically connected to an input of the K-bit latch portion.