Dual function compatible non-volatile memory device

• US 8,837,237 B2
• Filed: 09/13/2013
• Issued: 09/16/2014
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Lam, David
• Application Number:
  US14/026,359
• Publication Number:
  US 20140010022A1
• Time in Patent Office: 368 Days
• Field of Search: 365/191, 365/226, 365/233.5, 365/233.1, 365/230.01, 365/230.03, 711/167, 711/170, 711/105
• US Class Current: 365/191
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Claims

1. A memory device, comprising:

a plurality of ports, the plurality of ports including;

a first plurality of ports corresponding to a first operating mode of the memory device;

a second plurality of ports corresponding to a second operating mode of the memory device; and

a mode selection port configured to receive a mode selection input signal;

a first circuit for decoding a command signals received via the plurality of ports to provide first decoded signals corresponding to the first operating mode;

a second circuit for decoding the command signals received via the plurality of ports to provide second decoded signals corresponding to the second operating mode; and

a selector for passing one of the first decoded signals and the second decoded signals in response to the mode selection input signal received via the mode selection port.

2. The memory device of claim 1, further comprising control logic operable to:

receive the one of the first decoded signals and the second decoded signals passed by the selector;

generate, based on the one of the first decoded signals and the second decoded signals passed by the selector, control signals for performing specified operations in connected core circuitry.

3. The memory device of claim 2, wherein the specified operation comprise read operations.

4. The memory device of claim 2, wherein the specified operation comprise program operations.

5. The memory device of claim 1, wherein:

the first operating mode comprises a synchronous operating mode of the core circuitry; and

the second operating mode comprises an asynchronous operating mode of the core circuitry.

6. The memory device of claim 1, wherein the first plurality of ports include one or more ports of the second plurality of ports.

7. The memory device of claim 1, wherein the mode selection port is one of the first plurality of ports.

8. The memory device of claim 1, wherein the mode selection port is one of the second plurality of ports.

9. The memory device of claim 1, wherein the mode selection input signal comprises a voltage level.

10. The memory device of claim 9, further comprising a mode detector operable to generate a mode signal, the mode detector comprising:

a voltage detector for providing a status signal when a voltage supply has reached a predetermined level, and

mode logic coupled to the mode selection port for driving the mode signal from a first logic level to a second logic level in response to the status signal while the mode selection port is biased to a voltage level other than the voltage supply.