Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle
First Claim
1. A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a gate positioned between said first and second regions;
a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and
a substrate region configured to inject charge into said floating body region to maintain said state of the memory cell;
wherein an amount of charge injected into said floating body region is a function of a charge stored in said floating body region.
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Abstract
An exemplary semiconductor memory cell is provided to include: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a buried layer region in electrical contact with the floating body region, below the first and second regions, spaced apart from the first and second regions; and a substrate region configured to inject charge into the floating body region to maintain the state of the memory cell; wherein an amount of charge injected into the floating body region is a function of a charge stored in the floating body region.
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Citations
20 Claims
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1. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region configured to inject charge into said floating body region to maintain said state of the memory cell; wherein an amount of charge injected into said floating body region is a function of a charge stored in said floating body region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region positioned below said buried layer region; wherein applying a voltage to said substrate region results in at least two stable floating body charge levels. - View Dependent Claims (12, 13)
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14. A semiconductor memory array comprising:
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a plurality of said memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region; wherein said substrate region is commonly connected to at least two of said memory cells, and wherein said substrate region is configured to inject charge into said floating body region of each of said memory cells connected thereto, to maintain said state of the memory cells in parallel. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification