Methods and apparatus for data access by a reprogrammable circuit module

• US 8,838,873 B2
• Filed: 06/25/2012
• Issued: 09/16/2014
• Est. Priority Date: 06/15/2011
• Status: Active Grant

• Current Assignee: Ryft Systems, Inc. (Jacobs Solutions, Inc.)
• Original Assignee: Data Design Corporation
• Inventors: Giganti, John J., Huo, Andrew, Baum, Richard A., Cavallo, John M., Bresnan, Timothy P., Moses, Charles A., Siddalingaiah, Madhu
• Primary Examiner(s): Bansal, Gurtej
• Application Number:
  US13/532,319
• Publication Number:
  US 20120324149A1
• Time in Patent Office: 813 Days
• Field of Search: 711/2, 711/5, 711/170
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

In some embodiments, an apparatus includes a set of memory modules configured to store data and a reprogrammable circuit module operatively coupled to the set of memory modules. The reprogrammable circuit module is configured to receive, from a host device, information associated with a search request. The reprogrammable circuit module is configured to change from a first configuration to a second configuration in response to receiving the information. The reprogrammable circuit module is configured to retrieve at least a portion of the data stored at the set of memory modules associated with the second configuration. The reprogrammable circuit module is configured to generate a search result based on the portion of the data, and transmit the search result to the host device.

Claims

1. An apparatus, comprising:

a plurality of memory modules, each memory module from the plurality of memory modules configured to store data to be retrieved in a data match computation;

a reprogrammable circuit module configured to execute the data match computation, the reprogrammable circuit module configured to receive data to be computationally and actively matched;

a plurality of data channels, each data channel from the plurality of data channels operably coupling the reprogrammable circuit module to at least one memory module from the plurality of memory modules, the reprogrammable circuit module configured to retrieve (1) a first set of data stored at a first memory module from the plurality of memory modules via a first data channel from the plurality of data channels, and in parallel (2) a second set of data stored at a second memory module from the plurality of memory modules via a second data channel from the plurality of data channels, to produce retrieved data including the first set of data and the second set of data, the reprogrammable circuit module configured to store the retrieved data for a time period, the reprogrammable circuit module configured to computationally and actively compare, during the time period and entirely at the reprogrammable circuit module, the retrieved data with a representation of the data to be matched to produce matched data, the reprogrammable circuit module configured to send a result signal representing the matched data; and

a driver module operatively coupled to the reprogrammable circuit module, the reprogrammable circuit module configured to be modified by the driver module, the driver module configured to modify the reprogrammable circuit module, at a first time, to retrieve data based at least in part on a first keyword, the driver module configured to modify the reprogrammable circuit module, at a second time after the first time, to retrieve data based at least in part on a second keyword different from the first keyword.

2. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is included in a dual in-line memory module (DIMM).

3. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to retrieve data from the first memory module at substantially a same time as from the second memory module.

4. The apparatus of claim 1, wherein the reprogrammable circuit module is a Field Programmable Gate Array (FPGA).

5. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is a flash memory module.

6. The apparatus of claim 1, wherein the plurality of memory modules are removably coupled to a Peripheral Component Interconnect Express (PCIe) card including the reprogrammable circuit module.

7. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to generate a data match result based at least in part on the matched data, the data match result being different from the matched data.

8. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is associated with an address translation table configured to store a plurality of address pairs, the address translation table being located at the first memory module.

9. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is configured to store data having a plurality of addresses, the data to be computationally and actively matched does not include an address from the plurality of addresses.

10. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to computationally and actively compare the retrieved data without using a processor separate from the reprogrammable circuit module.

11. A method, comprising:

receiving a query associated with a data match computation;

retrieving a set of data, based at least in part on the query and during a first time period, from a first memory module from a plurality of memory modules via a first data channel, to produce first retrieved data including the set of data from the first memory module;

retrieving a set of data, based at least in part on the query, in parallel to the retrieving from the first memory module via the first data channel, and during a second time period overlapping the first time period, from a second memory module from the plurality of memory modules via a second data channel, to produce second retrieved data including the set of data from the second memory module;

storing, at a reprogrammable circuit module, the first retrieved data and the second retrieved data for a time period;

producing, during the time period, matched data by computationally and actively comparing, entirely at the reprogrammable circuit module, the first retrieved data and the second retrieved data to a representation of the query;

sending, to a compute device, a result signal representing the matched data;

retrieving data, at a first time, based at least in part on a first keyword and a communication from a driver module; and

retrieving data, at a second time after the first time, based at least in part on a second keyword different from the first keyword and a communication from the driver module.

12. The method of claim 11, wherein the first memory module is included within a common dual in-line memory module (DIMM) as the second memory module.

13. The method of claim 11, wherein the first memory module is a flash memory module.

14. The method of claim 11, further comprising:

generating a data match result based at least in part on the matched data, the data match result being different from the matched data.

15. The method of claim 11, wherein the first memory module and the second memory module are configured to store data having a plurality of addresses, the query associated with the data match computation does not include an address from the plurality of addresses.

16. An apparatus, comprising:

a plurality of memory modules, each memory module from the plurality of memory modules configured to store data to be retrieved;

a reprogrammable circuit module configured to receive data to be computationally and actively matched, the reprogrammable circuit module configured to retrieve a first set of data from a first memory module from the plurality of memory modules, and in parallel a second set of data from a second memory module from the plurality of memory modules to produce retrieved data, the retrieved data including the first set of data and the second set of data, the reprogrammable circuit module configured to store the retrieved data for a time period, the reprogrammable circuit module configured to computationally and actively compare, during the time period and entirely at the reprogrammable circuit module, the retrieved data with a representation of the data to be matched to produce matched data, the reprogrammable circuit module configured to send a result signal representing the matched data; and

a driver module operatively coupled to the reprogrammable circuit module, the reprogrammable circuit module configured to be modified by the driver module, the driver module configured to modify the reprogrammable circuit module, at a first time, to retrieve data based at least in part on a first keyword, the driver module configured to modify the reprogrammable circuit module, at a second time after the first time, to retrieve data based at least in part on a second keyword different from the first keyword.

17. The apparatus of claim 16, wherein the second memory module is different than the first memory module.

18. The apparatus of claim 16, wherein the driver module is configured to modify the reprogrammable circuit module, at a first time, to perform a first task, the driver module configured to modify the reprogrammable circuit module, at a second time after the first time, to perform a second task.

19. The apparatus of claim 16, wherein the reprogrammable circuit module is configured to generate a data match result based on the matched data, the data match result being different from the matched data.

20. The apparatus of claim 16, wherein each memory module from the plurality of memory modules is associated with an address translation table configured to store a plurality of address pairs, the address translation table being collocated with at least a portion of the data to be retrieved.