USB self-idling techniques

• US 8,839,016 B2
• Filed: 11/21/2012
• Issued: 09/16/2014
• Est. Priority Date: 07/23/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Zhang, Zhenyu, Jan, James Kang-Wuu, Huang, Frank, Jiang, Yong, Lin, Yui, Lo, Lite
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US13/683,056
• Publication Number:
  US 20130346777A1
• Time in Patent Office: 664 Days
• Field of Search: 713/300, 713/323, 713/324
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

USB self-idling techniques are described. In one or more embodiments, a Universal Serial Bus (USB) device comprises one or more modules to communicate via USB and self-idle by presenting an idle mode to a USB host and entering a suspend mode after the idle mode, the suspend mode being entered while the USB host is presented with the idle mode.

Claims

1. A Universal Serial Bus (USB) device including a USB device controller configured to:

communicate via a USB bus with a USB host capable of providing current to the USB device; and

present a first mode to the USB host and enter a second mode while presenting the first mode to the USB host by deactivating a clock device of the USB device, causing the USB device to ignore data packets communicated via the USB bus while in the second mode, and monitoring a power bus line of the USB bus effective to enable the USB device controller to detect a power cycle event on the USB bus.

2. The USB device of claim 1, wherein:

the first mode is an idle mode;

the second mode is a suspend mode; and

the presenting of the idle mode includes idling differential signal lines of the USB bus and is effective to prevent the USB host from limiting the current provided to the USB device to less than 100 mA while in the suspend mode.

3. A USB device as described in claim 1, wherein the second mode is entered in less than 3 milliseconds of presenting the first mode effective to avoid latency associated with a USB suspend protocol.

4. A USB device as described in claim 1, wherein the presenting of the first mode is effective to cause the USB host to provide about 500 mA of current to the USB device if the USB host is a high-power USB host or to provide about 100 mA of current to the USB device if the USB host is a low-power USB host.

5. A USB device as described in claim 1, wherein the presenting of the first mode is effective to cause the USB host to provide more than 2.5 mA of current to the USB device and enable the USB device to consume more than 2.5 mA of current while in the second mode.

6. A USB device as described in claim 1, wherein:

the clock device of the USB device is a phase-locked loop (PLL) clock; and

the entering of the second mode causes deactivation of the PLL clock.

7. A USB device as described in claim 1, wherein the entering of the second mode is effective to cause the USB device to monitor only the voltage supply line of the USB bus.

8. A USB device as described in claim 1, wherein the first mode presented to the USB host corresponds to high-speed operating mode instead of a full-speed or low-speed operating mode previously presented by the USB device.

9. A USB device as described in claim 1, wherein the USB device controller is further configured to cease to self-idle by leaving the second mode in response to the power cycle event.

10. A USB device as described in claim 1, wherein the USB device controller is further configured to cease to self-idle by leaving the second mode in response to reset of the USB bus.

11. A USB device as described in claim 1, wherein the USB device controller is further configured to wake the USB host using an out-of-band (OOB) signal or a general purpose input output (GPIO) signal.

12. A USB device as described in claim 1, wherein the USB device controller is further configured to:

communicate with an access point over a wireless local area network; and

poll the access point at predetermined intervals by waking the USB device from the second mode to determine if one or more packets are available for communication from the access point, wherein the waking and the determining are performed while the USB device continues to present the first mode to the USB host.

13. A method comprising:

presenting, at a port of a Universal Serial Bus (USB) device, a first mode to a USB host; and

causing the USB device to enter a second mode while presenting the first mode to the USB host, wherein;

causing the USB device to enter the second mode includes deactivating a clock device of the USB device and causing the USB device to ignore data packets communicated via the USB while in the second mode.

14. The method of claim 13, wherein:

the first mode is an idle mode;

the second mode is a suspend mode; and

the presenting of the idle mode includes idling differential signal lines of the USB bus and is effective to prevent the USB host from limiting the current provided to the USB device to less than 100 mA while in the suspend mode.

15. A method as described in claim 13, wherein the USB host is a high-power USB host and the presenting of the high-speed first mode is effective to cause the USB host to provide more than 2.5 mA of current to the USB device.

16. A method as described in claim 13, wherein the clock device of the USB device is a phase-locked loop (PLL) clock and entering the second mode causes deactivation of the PLL clock.

17. A method as described in claim 13, wherein the entering of the second mode further includes monitoring a power bus line of the USB bus effective to enable the USB device controller to detect a power cycle event on the USB bus.

18. A method as described in claim 13, wherein causing the USB device to ignore packets communicated via the USB bus includes causing the USB device to ignore a USB resume signal.

19. A method as described in claim 13, further comprising causing the USB device to leave the second mode in response to a power cycle event or in response to a reset of the USB bus.

20. A method as described in claim 13, further comprising:

providing a communicative association with an access point over a wireless local area network (WLAN); and

polling the access point at predetermined intervals by causing the USB device to wake from the second mode to determine if one or more packets are available for communication from the access point, wherein the waking and the determining are performed while the USB device is presenting the high-speed first mode to the USB host.