Method for determining transmission error due to a crosstalk between signal lines by comparing tuning pattern signals sent in parallel from a memory device with the tuning pattern signals pre-stored in a host device

• US 8,839,021 B2
• Filed: 08/08/2013
• Issued: 09/16/2014
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Akihisa
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Chen, Xuxing
• Application Number:
  US13/962,529
• Publication Number:
  US 20130326257A1
• Time in Patent Office: 404 Days
• Field of Search: 713/503
• US Class Current: 713/503
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Claims

1. A memory device comprising:

a non-volatile semiconductor memory;

a non-volatile memory side signal pattern storage configured to prestore a pattern of a first tuning signal and a pattern of a second tuning signal, the pattern of the first tuning signal and the pattern of the second tuning signal being sent to a host device to which the memory device is connected through signal lines; and

a memory controller configured to perform control for sending and receiving signals to and from the host device to which the memory device is connected through signal lines, the memory controller performing control to receive command signals through a command line, send response signals through the command line, and send and receive data signals through data lines in synchronization with a clock signal received through a clock line, and to perform control to send the first tuning signal through one signal line and send the second tuning signal through another signal line so that a time period during which the first tuning signal is sent and a time period during which the second tuning signal is sent overlap each other.

2. The memory device according to claim 1, wherein the pattern of the first tuning signal and the pattern of the second tuning signal are prestored also in the host device.

3. The memory device according to claim 2, wherein interference between the one signal line and the other signal line is detected by the host device.

4. The memory device according to claim 1, wherein the nonvolatile semiconductor memory unit is a NAND flash memory unit.

5. The memory device according to claim 1, which is a memory card.

6. A host device comprising:

a clock configured to generate a clock signal;

a host controller configured to perform control for sending signals to a memory device which is connected to the host device through signal lines and which has a non-volatile semiconductor memory unit, and to receive signals from the memory device in synchronization with a sampling clock signal, the sampling clock signal being the clock signal whose phase is adjusted, the host controller controlling sending of the clock signal through a clock line, sending of command signals through a command line, receiving of response signals through the command line, and sending and receiving of data signals through data lines;

a host side signal pattern storage unit configured to store a pattern of a first tuning signal and a pattern of a second tuning signal;

a host processor configured to compare patterns of the first tuning signal received through one signal line and second tuning signal received through another signal line in a time period overlapping a time period during which the first tuning signal is received with the patterns stored in the host side signal pattern storage unit; and

a sampling clock adjustment unit configured to adjust a phase of the sampling clock signal based on a result of the comparison between the pattern of the first tuning signal received through the one signal line and the pattern of the second tuning signal received through the another signal line in a time period overlapping a time period during which the first tuning signal is received and the patterns are stored in the host side signal pattern storage unit.

7. The host device according to claim 6, wherein the sampling clock adjustment unit generates a plurality of oversampling clock signals whose phases are different, and uses one oversampling clock signal selected from the plurality of oversampling clock signals as the sampling signal after phase adjustment.

8. The host device, according to claim 6, wherein the sampling clock adjustment unit adjusts the phase of the sampling clock signal at least twice.

9. The host device according to claim 6, wherein the host controller changes sending and receiving conditions of the signals based on a result of the comparison.

10. The host device according to claim 9, wherein the sending and receiving conditions are frequency of the clock signal and the sampling clock signal.

11. The host device according to claim 6, wherein the nonvolatile semiconductor memory of the memory device is a NAND flash memory unit.

12. The host device according to claim 6, wherein the memory device is a memory card.