Initialization of GPU using ROM-based initialization unit and programmable microcontroller

• US 8,839,039 B2
• Filed: 01/24/2012
• Issued: 09/16/2014
• Est. Priority Date: 01/24/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Garlick, Lincoln, Jamkar, Saket, Mueller, Steven
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US13/357,553
• Publication Number:
  US 20130191692A1
• Time in Patent Office: 966 Days
• Field of Search: None
• US Class Current: 714/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06F 2221/2147 Locking files
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems

Abstract

An approach is disclosed for performing initialization operations for a graphics processing unit (GPU). The approach includes detecting errors while performing one or more initialization operations. Further, the approach includes releasing a holdoff on a communication link that couples the GPU to a memory bridge and causing debug output to be displayed to a user that indicates the error.

Claims

1. A computer-implemented method for performing initialization operations for a graphics processing unit (GPU), the method comprising:

detecting an error while performing one or more initialization operations;

releasing a holdoff on a communication link that couples the GPU to a memory bridge; and

causing debug output to be displayed to a user that indicates the error.

2. The method of claim 1, wherein the communication link comprises a Peripheral Component Interconnect Express (PCIe) link.

3. The method of claim 1, wherein releasing the holdoff comprises terminating a first initialization unit, unless releasing the holdoff on the communication link has been assigned to a second initialization unit.

4. The method of claim 1, wherein the error comprises at least one of a read-only memory (ROM) that includes initialization instructions not being found, a signature of the ROM not matching a predefined signature, a total size of the ROM not matching a predefined size, a checksum value based on a plurality of bits included in the ROM not matching a predefined value, a parity value based on a plurality of bits included in the ROM not matching a predefined value, a size of instructions having been read exceeding the total size of the ROM, or the size of instructions having been read plus a size of any required last instruction or instructions exceeding the total size of the ROM.

5. The method of claim 1, wherein the error comprises at least one of a parity value associated with an instruction read from a ROM that includes initialization instructions not matching a predefined parity for bits composing some or all of the instruction, bits within the instruction that do not match predefined values for those bits, or a number of dwords of the instruction not matching a predefined number.

6. The method of claim 1, further comprising programming, by operation of a first initialization unit, a second initialization unit to perform at least one of the one or more initialization operations, allowing for at least one initialization operation not being a predefined operation conceived before hardware fabrication.

7. The method of claim 6, wherein the second initialization unit comprises a microcontroller, and wherein programming the second initialization unit comprises performing one or more of a read-modify-write operation, repeated write operations to the same address, or write operations to incrementing addresses.

8. The method of claim 7, wherein the one or more initialization operations comprise at least one of a polling operation, a branching operation, repeated access operations to a resource, or a delay operation.

9. The method of claim 8, wherein the first initialization unit and the second initialization unit perform different initialization operations concurrently.

10. An initialization unit of a graphics card configured to:

detect an error while performing one or more initialization operations;

release a holdoff on a communication link in response to the detected error; and

cause debug output to be displayed to a user that indicates the error.

11. The initialization unit of claim 10, wherein the communication link comprises a Peripheral Component Interconnect Express (PCIe) link.

12. The initialization unit of claim 10, wherein releasing the holdoff comprises terminating a first initialization unit, unless releasing the holdoff on the communication link has been assigned to a second initialization unit.

13. The initialization unit of claim 10, wherein the error comprises at least one of a read-only memory (ROM) that includes initialization instructions not being found, a signature of the ROM not matching a predefined signature, a total size of the ROM not matching a predefined size, a checksum value based on a plurality of bits included in the ROM not matching a predefined value, a parity value based on a plurality of bits included in the ROM not matching a predefined value, a size of instructions having been read exceeding the total size of the ROM, or the size of instructions having been read plus a size of any required last instruction or instructions exceeding the total size of the ROM.

14. The initialization unit of claim 10, wherein the error comprises at least one of a parity value associated with an instruction read from a ROM that includes initialization instructions not matching a predefined parity for bits composing some or all of the instruction, bits within the instruction that do not match predefined values for those bits, or a number of dwords of the instruction not matching a predefined number.

15. The initialization unit of claim 10, wherein the initialization unit is further configured to program a second initialization unit to perform at least one of the one or more initialization operations, allowing for at least one initialization operation not being a predefined operation conceived before hardware fabrication.

16. The initialization unit of claim 15, wherein the second initialization unit comprises a microcontroller, and wherein programming the second initialization unit comprises performing one or more of a read-modify-write operation, repeated write operations to the same address, or write operations to incrementing addresses.

17. The initialization unit of claim 16, wherein the one or more initialization operations comprise at least one of a polling operation, a branching operation, repeated access operations to a resource, or a delay operation.

18. The initialization unit of claim 17, wherein the initialization unit is further configured to offload at least one initialization operation to the second initialization unit, and wherein the initialization unit and the second initialization unit perform respective initialization operations concurrently.

19. A computing device comprising:

a graphics processing unit (GPU) having an initialization unit, wherein the initialization unit is configured to;

detect an error while performing one or more initialization operations;

release a holdoff on a communication link that couples the GPU to a memory bridge; and

cause debug output to be displayed to a user that indicates the error.

20. The computing device of claim 19, wherein the initialization unit is further configured to program a microcontroller to perform at least one of the one or more initialization operations, allowing for at least one initialization operation not being a predefined operation conceived before hardware fabrication.