Semiconductor memory devices that are configured to analyze read failures and related methods of operating such devices

• US 8,839,071 B2
• Filed: 11/21/2008
• Issued: 09/16/2014
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jo, Sung-Kyu
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US12/275,470
• Publication Number:
  US 20090164871A1
• Time in Patent Office: 2,125 Days
• Field of Search: 714/763, 714/773
• US Class Current: 714/763
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed.

Claims

1. A semiconductor memory device comprising:

a nonvolatile memory that includes a plurality of memory cells;

an error correction unit; and

a controller that is configured to;

determine, using an output of the error correction unit, that a read failure occurred during a read operation of a first of the plurality of memory cells;

determine, by changing a selective read voltage, whether the read failure resulted because the first of the plurality of memory cells was programmed with data having a first value but was sensed as storing data having a second value or because the first of the plurality of memory cells was programmed with data having the second value but was sensed as storing data having the first value; and

repair the read failure if it is due to charge leakage or to soft-programming by re-programming, and to repair the read failure if it is due to over-programming by increasing a non-selective read voltage.

2. The semiconductor memory device as set forth in claim 1, wherein the controller is further configured to increase a selective read voltage and perform a second read operation on the first of the plurality of memory cells if it is determined that the first of the plurality of memory cells was programmed with data having the first value but was sensed as storing data having the second value.

3. The semiconductor memory device as set forth in claim 1, wherein the controller is further configured to determine if the read failure is due to soft-programming by increasing a selective read voltage and performing a second read operation on the first of the plurality of memory cells.

4. The semiconductor memory device as set forth in claim 3, wherein the controller is further configured to identify the read failure as being caused by soft-programming when a second read failure does not occur during the second read operation, and is also configured to identify the read failure as being caused by over-programming when the second read failure occurs during the second read operation.

5. The semiconductor memory device as set forth in claim 1, wherein data having the first value comprises data having a value of “

1” and

data having the second value comprises data having a value of “

0.”

6. The semiconductor memory device as set forth in claim 1, wherein the controller is further configured to repair the first of the plurality of memory cells by a charge refresh operation when the output of the error correction unit indicates that the first of the plurality of memory cells was programmed with data having the second value but was sensed as storing data having the first value.

7. A method for analyzing a read failure that occurred during a first data read operation of a first memory cell of a nonvolatile memory of a semiconductor memory device, the method comprising:

analyzing error correction code data that is associated with data that was read from the nonvolatile memory during the first data read operation to determine a cause of the read failure from one of a plurality of possible causes for the read failure, wherein the cause of the read failure is determined based at least in part on a value that was programmed into the first memory cell that was incorrectly sensed during the first data read operation; and

repairing the read failure by re-programming if the cause of the read failure is determined to be either charge leakage or soft-programming, and repairing the read failure by increasing a non-selective read voltage if the cause of the read failure is determined to be over-programming.

8. The method as set forth in claim 7, the method further comprising:

increasing a selective read voltage that was used in the first data read operation;

performing a second read operation using the increased selective read voltage to determine whether the read failure resulted because of soft-programming.

9. The method as set forth in claim 8, further comprising identifying the read failure as being caused by soft-programming if a second read failure does not occur during the second read operation.

10. The method as set forth in claim 8, further comprising identifying the read failure as being caused by over-programming if a second read failure occurs during the second read operation.