Self-aligned double patterning via enclosure design

• US 8,839,168 B2
• Filed: 01/22/2013
• Issued: 09/16/2014
• Est. Priority Date: 01/22/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kye, Jongwook, Yuan, Lei, Levinson, Harry J, Stephens, Jason E
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/746,508
• Publication Number:
  US 20140208285A1
• Time in Patent Office: 602 Days
• Field of Search: 716/100, 716/110
• US Class Current: 716/110
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Claims

1. A method for computing via enclosure rules, comprising:

identifying, by at least one computing device, line termination modes in a self-aligned double patterning line pattern comprising a plurality of lines and vias;

assigning, by the at least one computing device, a first via enclosure rule in response to identifying a line termination mode of inner vertex block mask, wherein the inner vertex block mask comprises at least one vertex that has an outer angle that is less than 180 degrees; and

assigning, by the at least one computing device, a second via enclosure rule in response to identifying a line termination mode of outer vertex block mask, wherein the outer vertex block mask consists of vertices that have an outer angle that is greater than 180 degrees.

2. The method of claim 1, wherein assigning a first via enclosure rule comprises assigning a first margin, and wherein assigning a second via enclosure rule comprises assigning a second margin.

3. The method of claim 2, wherein the first margin is larger than the second margin.

4. The method of claim 3, wherein the first margin is about two to three times larger than the second margin.

5. The method of claim 3, wherein the first margin ranges from about 8 nanometers to about 12 nanometers, and wherein the second margin ranges from about 28 nanometers to about 32 nanometers.

6. The method of claim 2, further comprising assigning a third via enclosure rule in response to identifying a line termination mode of mandrel.

7. The method of claim 6, wherein assigning a third via enclosure rule comprises assigning a third margin.

8. The method of claim 7, wherein the third margin is equal to the first margin.

9. The method of claim 1, wherein identifying a line termination mode of outer vertex block mask comprises identifying a rectangular block mask.

10. The method of claim 1, wherein identifying a line termination mode of inner vertex block mask comprises identifying an L-shaped block mask.

11. The method of claim 1, wherein identifying a line termination mode of inner vertex block mask comprises identifying a U-shaped block mask.

12. A method for computing via enclosure rules, comprising:

identifying, by at least one computing device, line termination modes in a self-aligned double patterning line pattern comprising a plurality of lines and vias;

assigning, by the at least one computing device, a first via enclosure rule in response to identifying a set of aligned adjacent lines; and

assigning, by the at least one computing device, a second via enclosure rule in response to identifying a set of misaligned adjacent lines.

13. The method of claim 12, wherein assigning a first via enclosure rule comprises assigning a first margin, and wherein assigning a second via enclosure rule comprises assigning a second margin.

14. The method of claim 13, wherein the second margin is larger than the first margin.

15. The method of claim 14, wherein the second margin is about two to three times larger than the first margin.

16. A non-transitory computer-readable medium comprising instructions which, when executed by a processor, perform the steps of:

identifying line termination modes in a self-aligned double patterning line pattern comprising a plurality of lines and vias;

assigning a first via enclosure rule in response to identifying a line termination mode of inner vertex block mask, wherein the inner vertex block mask comprises at least one vertex that has an outer angle that is less than 180 degrees; and

assigning a second via enclosure rule in response to identifying a line termination mode of outer vertex block mask, wherein the outer vertex block mask consists of vertices that have an outer angle that is greater than 180 degrees.

17. The computer-readable medium of claim 16, further comprising instructions which, when executed by a processor, perform the steps of:

assigning a first margin corresponding to the first via enclosure rule; and

assigning a second margin corresponding to the second via enclosure rule.

18. The computer-readable medium of claim 16, further comprising instructions which, when executed by a processor, perform the step of assigning a third via enclosure rule in response to identifying a line termination mode of mandrel.

19. The computer-readable medium of claim 17, further comprising instructions which, when executed by a processor, perform the step of assigning the first margin as larger than the second margin.

20. The computer-readable medium of claim 19, further comprising instructions which, when executed by a processor, perform the step of assigning the first margin as about two to three larger than the second margin.