Method and system allowing for semiconductor design rule optimization

• US 8,839,177 B1
• Filed: 08/22/2013
• Issued: 09/16/2014
• Est. Priority Date: 08/22/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bickford, Jeanne P., Landis, Howard S., Styduhar, Mark S., Aubel, Mark D., Ross, Michael T., Windisch, Charles H. Jr.
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/972,965
• Time in Patent Office: 390 Days
• Field of Search: 716/100, 716/132
• US Class Current: 716/132
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes. Optionally, each hybrid fill-placeable library element comprises different fill shapes at different levels and corresponding to different features so that it can be employed to meet multiple different density rules.

Claims

1. A method comprising:

accessing, by a computer-aided design system, a library stored in a memory, said library comprising functional library elements and hybrid fill-placeable library elements; and

placing, by said computer-aided design system, both selected functional library elements and at least one selected hybrid fill-placeable library element in a layout of an integrated circuit chip under design,

said selected hybrid fill-placeable library element being placed in said layout in order to meet, at one of a tile-level and a product-level, a first density rule directed to first features when any of said selected functional library elements violates said first density rule, and

said selected hybrid fill-placeable library element comprising;

first fill shapes corresponding to said first features; and

a corresponding marker shape comprising an instruction that is executable by said computer-aided design system during design rule checking and that defines a custom design rule for said selected hybrid fill-placeable library element.

2. The method of claim 1,

said selected hybrid fill-placeable library element also being placed in said layout in order to meet, at said one of said tile-level and said product-level, a second density rule directed to second features when said any of said selected functional library elements violates said second density rule, and

said selected hybrid fill-placeable library element further comprising second fill shapes corresponding to said second features.

3. The method of claim 2, said first features and said second features comprising any of two of deep trenches, diffusion regions, local interconnect features, polysilicon features, metal features, and via interconnect features.

4. The method of claim 2,

said selected hybrid fill-placeable library element also being placed in said layout in order to meet, at said one of said tile-level and said product-level, a third density rule directed to third features when said any of said selected functional library elements violates said third density rule,

said selected hybrid fill-placeable library element further comprising third fill shapes corresponding to said third features,

said first features, said second features, and said third features comprising any of three of deep trenches, diffusion regions, polysilicon features, local interconnect features, metal features, and via interconnect features.

5. The method of claim 1, said designing comprising:

executing a placement algorithm that defines locations for said selected hybrid fill-placeable library elements within a gate array on said integrated circuit chip in order to meet feature density rules; and

replacing gate array base cells in said gate array at said locations with said selected hybrid fill-placeable library elements, said selected hybrid fill-placeable library elements and said gate array base cells being compatible in size to allow for said replacing.

6. The method of claim 5, said designing comprising executing a placement algorithm that defines locations for said hybrid fill-placeable library elements adjacent to said selected functional library elements in order to meet said feature density rules.

7. The method of claim 1, said hybrid fill-placeable library elements each comprising product-level power and ground through line shapes allowing for integration with said functional library elements.

8. A computer-aided design system comprising:

a memory storing a library comprising functional library elements and hybrid fill-placeable library elements; and

at least one processor accessing said library and placing, in a layout of an integrated circuit chip, both selected functional library elements and at least one selected hybrid fill-placeable library element,

said selected hybrid fill-placeable library element being placed in said layout in order to meet, at one of a tile-level and a product-level, a first density rule for first features when any of said selected functional elements violates said first density rule, and

said selected hybrid fill-placeable library element comprising;

first fill shapes corresponding to said first features; and

a corresponding marker shape comprising an instruction that is executable by said processor during design rule checking and that defines a custom design rule for said selected hybrid fill-placeable library element.

9. The system of claim 8,

said selected hybrid fill-placeable library element also being placed in said layout in order to meet, at said one of said tile-level and said product-level, a second density rule directed to second features when said any of said selected functional library elements violates said second density rule, and

said selected hybrid fill-placeable library element further comprising second fill shapes corresponding to said second features.

10. The system of claim 9, said first features and said second features comprising any of two of deep trenches, diffusion regions, polysilicon features, local interconnect features, metal features, and via interconnect features.

11. The system of claim 9,

said selected hybrid fill-placeable library element also being placed in said layout in order to meet, at said one of said tile-level and said product-level, a third density rule directed to third features when said any of said selected functional library elements violates said third density rule,

said selected hybrid fill-placeable library element further comprising third fill shapes corresponding to said third features, and

said first features, said second features, and said third features comprising any of three of deep trenches, diffusion regions, polysilicon features local interconnect features, metal features, and via interconnect features.

12. The system of claim 8, said designing comprising:

executing a placement algorithm that defines locations for said selected hybrid fill-placeable library elements within a gate array on said integrated circuit chip in order to meet feature density rules; and

replacing gate array base cells in said gate array at said locations with said selected hybrid fill-placeable library elements, said selected hybrid fill-placeable library elements and said gate array base cells being compatible in size to allow for said replacing.

13. The system of claim 8, said designing comprising executing a placement algorithm that defines locations for said hybrid fill-placeable library elements adjacent to said selected functional library elements in order to meet feature density rules.

14. The system of claim 8, said hybrid fill-placeable library elements each comprising product-level power and ground through line shapes allowing for integration with said functional library elements.

15. A hybrid fill-placeable library element in a library stored on a computer-readable storage medium and accessible by a computer-aided design system during integrated circuit design,

said hybrid fill-placeable library element being selectable, by said computer, for placement in a layout of an integrated circuit chip under design in order to meet, at one of a tile-level and a product-level, a first density rule directed to first features when any functional library elements placed in said layout violate said first density rule, and

said hybrid fill-placeable library element comprising:

first fill shapes corresponding to said first features; and

a corresponding marker shape comprising an instruction that is executable by said computer-aided design system during design rule checking and that defines a custom design rule for said hybrid fill-placeable library element.

16. The hybrid fill-placeable library element of claim 15,

said hybrid fill-placeable library element further being selectable, by said computer, for placement in said layout in order to meet, at said one of said tile-level and said product-level, a second density rule directed to second features when said any functional library elements placed in said layout violate said second density rule, and

said hybrid fill-placeable library element further comprising second fill shapes corresponding to said second features.

17. The hybrid fill-placeable library element of claim 16, said first features and said second features comprising any of two of deep trenches, diffusion regions, polysilicon features, local interconnect features, metal features, and via features.

18. The hybrid fill-placeable library element of claim 16,

said hybrid fill-placeable library element further being selectable, by said computer, for placement in said layout in order to meet, at said one of said tile-level and said product-level, a third density rule directed to third features when said any functional library elements placed in said layout violate said third density rule, and

said hybrid fill-placeable library element further comprising third fill shapes corresponding to said third features.

19. The hybrid fill-placeable library element of claim 18, said first features, said second features, and said third features comprising any of three of deep trenches, diffusion regions, polysilicon features, local interconnect features, metal features, and via features.

20. The said hybrid fill-placeable library element of claim 15, further comprising product-level power and ground through line shapes allowing for integration with said functional library elements.