Prototype and emulation system for multiple custom prototype boards

• US 8,839,179 B2
• Filed: 04/03/2013
• Issued: 09/16/2014
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Taiwan Co., Ltd. (Synopsys Incorporated)
• Inventors: Chang, Yingtsai, Shei, Sweyyan, Chiu, Hung-Chun, Lin, Meng-Chyi, Mao, Hwa, Wang, Ming Yang, Hsu, Yuchin
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/856,004
• Publication Number:
  US 20130227509A1
• Time in Patent Office: 531 Days
• Field of Search: 716/105, 716/106, 716/108, 716/111, 716/116, 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.

Claims

1. A test system, comprising:

a host workstation configured to divide a user design into a plurality of design partitions and to generate a plurality of verification modules, wherein each verification module is associated with one of the design partitions;

a first interface device coupled to the host workstation and configured to receive the design partitions and the associated verification modules from the host workstation; and

a second interface device and a third interface device each coupled to the first interface device, wherein the second interface device and the third interface device are collectively configured to receive the design partitions and the associated verification modules from the first interface device, wherein the second interface device is configured to receive at least one of the design partitions and at least one associated verification module from the first interface device, and wherein the third interface device is configured to receive at least one of the design partitions and at least one associated verification module from the first interface device,

wherein the second interface device is configured to connect to a first prototype board which is programmable, and to program the first prototype board with the at least one design partition and associated verification module received by the second interface device,

wherein the third interface device is configured to connect to a second prototype board which is programmable, and to program the second prototype board with the at least one design partition and associated verification module received by the third interface device.

2. The test system of claim 1, wherein the second interface device comprises a memory configured to store first input vectors for the design partitions of the first prototype board and the second interface device is configured to transmit the first input vectors to the design partitions of the first prototype board to exercise the user design, and wherein the third interface device comprises a memory configured to store second input vectors for the design partitions of the second prototype board and the third interface device is configured to transmit the second input vectors to the design partitions of the second prototype board to exercise the user design.

3. The test system of claim 1, wherein each verification module is configured to probe signals from the design partition associated therewith, and wherein the verification modules of the first prototype board are configured to transmit the probed signals thereof to the second interface device and the verification modules of the second prototype board are configured to transmit the probed signals thereof to the third interface device.

4. The test system of claim 3, wherein the second interface device comprises a memory configured to store probed signals from the first prototype board, and the third interface device comprises a memory figure to store probed signals from the second prototype board.

5. The test system of claim 3, wherein the second interface device is configured to transmit one or more probed signals from the first prototype board to the first interface device, and the third interface device is configured to transmit one or more probed signals from the second prototype board to the first interface device.

6. The test system of claim 5, wherein the first interface device is configured to generate a trigger signal based on the probed signals from the first prototype board and the second prototype board, to transmit the trigger signal to the first prototype board through the second interface device, and to transmit the trigger signal to the second prototype board through the third interface device.

7. The test system of claim 6, wherein the trigger signal communicates timing information coordinating the operation of storing the probed signals into the memory on the second interface device and the memory on the third interface device.

8. A test system, comprising:

a host workstation configured to divide a user design into a plurality of first design partitions and to generate a plurality of first verification modules, wherein each first verification module is associated with one of the first design partitions, wherein the host workstation is further configured to divide the user design into a plurality of second design partitions and to generate a plurality of second verification modules, and wherein each second verification module is associated with one of the second design partitions;

a first interface device coupled to the host workstation and configured to receive the first design partitions and the associated first verification modules from the host workstation, wherein the first interface device is configured to connect to a first prototype board which is programmable, and to program the first prototype board with the first design partitions and the associated first verification modules; and

a second interface device coupled to the host workstation and configured to receive the second design partitions and the associated second verification modules from the host workstation, wherein the second interface device is configured to connect to a second prototype board which is programmable, and to program the second prototype board with the second design partitions and the associated second verification modules.

9. The test system of claim 8, wherein the first interface device comprises a memory configured to store first input vectors for the first design partitions and the first interface device is configured to transmit the first input vectors to the first design partitions to exercise the user design, and wherein the second interface device comprises a memory configured to store second input vectors for the second design partitions and the second interface device is configured to transmit the second input vectors to the second design partitions to exercise the user design.

10. The test system of claim 8, wherein each verification module is configured to collect output signals from the design partition associated therewith, and wherein the first verification modules of the first prototype board are configured to transmit first output signals to the first interface device and the second verification modules of the second prototype board are configured to transmit second output signals to the second interface device.

11. The test system of claim 10, wherein the first interface device is configured to transmit one or more first output signals to the host workstation, and the second interface device is configured to transmit one or more second output signals to the host workstation, and wherein the host workstation is configured to generate input signals based on the first output signals and the second output signals and to transmit the input signals to the first prototype board and the second prototype board through the first interface device and the second interface device, respectively.

12. The test system of claim 11, wherein the first prototype board and the second prototype board are configured to receive the input signals from the host workstation, to respectively generate first output signals and second output signals based on the received input signals, and to respectively transmit the first output signals and the second output signals to the host workstation through the first interface device and the second interface device.

13. A test system, comprising:

a host workstation configured to divide a first user design into a plurality of first design partitions and to generate a plurality of first verification modules, wherein each first verification module is associated with one of the first design partitions, wherein the host workstation is further configured to divide a second user design into a plurality of second design partitions and to generate a plurality of second verification modules, wherein each second verification module is associated with one of the second design partitions;

a first interface device coupled to the host workstation and configured to receive the first design partitions and the associated first verification modules from the host workstation, wherein the first interface device is configured to connect to a first prototype board which is programmable, and to program the first prototype board with the first design partitions and the associated first verification modules; and

a second interface device coupled to the host workstation and configured to receive the second design partitions and the associated second verification modules from the host workstation, wherein the second interface device is configured to connect to a second prototype board which is programmable, and to program the second prototype board with the second design partitions and the associated second verification modules.

14. The test system of claim 13, wherein the first interface device comprises a memory configured to store first input vectors for the first design partitions and the first interface device is configured to transmit the first input vectors to the first design partitions to exercise the first user design, and wherein the second interface device comprises a memory configured to store second input vectors for the second design partitions and the second interface device is configured to transmit the second input vectors to the second design partitions to exercise the second user design.

15. The test system of claim 13, wherein each verification module is configured to probe signals from the design partition associated therewith, and wherein the first verification modules of the first prototype board are configured to transmit first probed signals to the first interface device and the second verification modules of the second prototype board are configured to transmit second probed signals to the second interface device.

16. The test system of claim 15, wherein the first interface device comprises a memory configured to store the first probed signals, and the second interface device comprises a memory figure to store the second probed signals.

17. The test system of claim 16, wherein the first prototype board and the second prototype board are respectively configured to receive first input signals and second input signals from the host workstation, to respectively generate first output signals and second output signals based on the received first input signals and the received second input signals, and to respectively transmit the first output signals and the second output signals to the host workstation through the first interface device and the second interface device.