Load balancing for multi-threaded applications via asymmetric power throttling

• US 8,839,258 B2
• Filed: 01/20/2012
• Issued: 09/16/2014
• Est. Priority Date: 12/30/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rakvic, Ryan, Hankins, Richard A., Grochowski, Ed, Wang, Hong, Annavaram, Murali, Poulsen, David K., Shah, Sanjiv, Shen, John, Chinya, Gautham
• Primary Examiner(s): An, Meng
• Assistant Examiner(s): LEE, TAMMY EUNHYE
• Application Number:
  US13/354,623
• Publication Number:
  US 20120131366A1
• Time in Patent Office: 970 Days
• Field of Search: None
• US Class Current: 718/102
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Claims

1. A non-transitory machine-accessible storage medium including instructions that, when executed by a machine, cause the machine to perform a method comprising:

determining a first execution time of a first thread of a process previously executed on a first processing unit of a multiprocessor;

determining a second execution time of a second thread of the process previously executed on a second processing unit of the multiprocessor;

adjusting a first power to the first processing unit and a second power to the second processing unit according to the first and second execution times of the first and second threads, wherein adjusting the first and second powers is for future execution of the same first and second threads of the process; and

wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.

2. The non-transitory machine-accessible storage medium of claim 1, wherein adjusting the first and second powers to the first and second processing units respectively includes:

increasing the first power provided to the first processing unit at a future execution of the first thread in response to the first execution time being greater than the second execution time.

3. The non-transitory machine-accessible storage medium of claim 1, wherein adjusting the first and second powers to the first and second processing units respectively includes:

decreasing the second power provided to the second processing unit at a future execution of the second thread in response to the first execution time being greater than the second execution time.

4. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising:

maintaining same power to the first and second processing units at future executions of the first and second threads in response to the first and second execution times being the same.

5. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising:

independently adjusting the first and second powers for each of the first and second processing units.

6. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising:

waiting for a period of time before adjusting the first and second powers.

7. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising:

halting load balancing when a number of attempts for load balancing exceed a threshold.

8. The non-transitory machine-accessible storage medium of claim 1, wherein adjusting the first power to the first processing unit and the second power to the second processing unit is to effectuate the first and second threads of the process to finish executing at approximately the same time in future executions of the first and second threads of the process.

9. The non-transitory machine-accessible storage medium of claim 8, wherein the future executions of the first and second threads being on the first and second processors of the multiprocessor respectively.

10. The non-transitory machine-accessible storage medium of claim 1 having further instructions to perform a further method comprising:

determining N execution times of N threads executing on N processing units of the multiprocessor, wherein the N threads are in addition to the first and second threads; and

maintaining same power to the N processing units in response to the N execution times being between the first and second execution times.

11. The non-transitory machine-accessible storage medium of claim 10, wherein the method is performed on a subset of the N threads.

12. The non-transitory machine-accessible storage medium of claim 1, wherein adjusting the first and second powers comprises adjusting the first and second powers by a predetermined amount.

14. The non-transitory machine-accessible storage medium of claim 1, wherein the instructions are to be executed in at least one of:

a user-level runtime environment or kernel layer.

13. A method comprising:

determining a first execution time of a first thread of a process previously executed on a first processing unit of a multiprocessor;

determining a second execution time of a second thread of the process previously executed on a second processing unit of the multiprocessor;

adjusting a first power to the first processing unit and a second power to the second processing unit according to the first and second execution times of the first and second threads, wherein adjusting the first and second powers is for future execution of the same first and second threads of the process; and

wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.

15. A multiprocessor comprising:

a first processing unit to operate at a first power; and

a second processing unit to operate at a second power;

wherein an asymmetric power throttling module to cause adjustment of the first power to the first processing unit and the second power to the second processing unit according to first and second execution times of previously executed first and second threads of a process, wherein the first and second threads are previously executed on the first and second processing units respectively,

wherein the adjustment of the first and second powers is for future execution of the same first and second threads of the process; and

wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.

16. The multiprocessor of claim 15 further comprises a power control unit which is operable to adjust the first and second powers to the corresponding first and second processing units.

17. The multiprocessor of claim 15 further comprises one or more logic units to determine the first and second execution times of the first and second threads of the process.

18. The multiprocessor of claim 15, wherein the asymmetric power throttling module to increase power provided to the first processing unit and to decrease power provided to the second processing unit in response to the first execution time of the first thread being substantially greater than the second execution time of a second thread.

19. The multiprocessor of claim 15, wherein the asymmetric power throttling module to cause the first and second processing units to maintain same power to the first and second processing units at future executions of the first and second threads in response to the first and second execution times being the same.

20. The multiprocessor of claim 15, wherein the asymmetric power throttling module is implemented at least in one of:

a hardware logic or in an operating system.

21. The multiprocessor of claim 15, wherein the first and second processing units are positioned in a single die.

22. The multiprocessor of claim 15 further comprises logic to delay adjusting of the first and second powers.

23. The multiprocessor of claim 15, wherein the first and second processing units implement at least one or more of:

simultaneous multi-threading or symmetric processing.

24. A computer system comprising:

a network communication interface; and

a multiprocessor coupled to the network communication interface, the multiprocessor including;

a first processing unit to operate at a first power;

a second processing unit to operate at a second power;

wherein an asymmetric power throttling module to cause adjustment of the first power to the first processing unit and the second power to the second processing unit according to first and second execution times of previously executed first and second threads of a process, wherein the first and second threads previously executed on the first and second processing units respectively, and wherein the adjustment of the first and second powers is for future execution of the same first and second threads of the process; and

wherein the adjusted first and second powers have a total power value below or equal to a total power budget for the multiprocessor.

25. The computer system of claim 24, wherein the multiprocessor further comprises a power control unit operable to adjust the first and second powers to the corresponding first and second processing units.

26. The computer system of claim 24, wherein the asymmetric power throttling module to increase power provided to the first processing unit and to decrease power provided to the second processing unit in response to the first execution time of the first thread being substantially greater than the second execution time of a second thread.

27. The computer system of claim 24, wherein the asymmetric power throttling module to cause the first and second processing units to maintain same power to the first and second processing units at future executions of the first and second threads in response to the first and second execution times being the same.

28. The computer system of claim 24, wherein the asymmetric power throttling module is implemented at least in one of:

a hardware logic or in an operating system.

29. The computer system of claim 24, wherein the first and second processing units are positioned in a single die.