Memory element and method for manufacturing the same, and semiconductor device

• US 8,841,642 B2
• Filed: 11/14/2007
• Issued: 09/23/2014
• Est. Priority Date: 11/17/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yoshizumi, Kensuke
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/939,702
• Publication Number:
  US 20100283024A1
• Time in Patent Office: 2,505 Days
• Field of Search: 257/2, 257/296, 257/529, 977/773
• US Class Current: 257/2
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: Y10S 977/773 Nanoparticle, i.e. structure having three dimensions of 100 nm or less

Abstract

The memory element has a structure at least including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer is formed by a droplet discharge method using nanoparticles of a conductive material each of which is coated with an organic thin film. Specifically, a composition in which nanoparticles of a conductive material each of which is coated with an organic thin film are dispersed in a solvent is discharged (ejected) as ink droplets, and the solvent is dried to be vaporized to form the memory layer. Accordingly, a memory element can be formed simply. In addition, efficiency in the use of materials can be improved and yield is also improved, so that the memory element can be provided at low cost.

Claims

1. A semiconductor device comprising a memory element comprising:

a first conductive layer over an insulating surface;

a second conductive layer over the first conductive layer; and

a memory layer interposed between the first conductive layer and the second conductive layer,

wherein the memory layer comprises nanoparticles each of which is coated with an organic thin film,

wherein the nanoparticles comprise a conductive material,

wherein the organic thin film comprises a surfactant, and

wherein the memory element is configured to be written a data by being applied a write voltage to break at least a part of the organic thin film so that at least a part of the nanoparticles contact with each other.

2. The semiconductor device according to claim 1,

wherein grain diameters of the nanoparticles are 1 nm to 200 nm.

3. The semiconductor device according to claim 1,

wherein the memory element is connected to a thin film transistor over a glass substrate or a flexible substrate.

4. The semiconductor device according to claim 1,

wherein the semiconductor device further comprises a third conductive layer serving as an antenna and a circuit comprising a transistor, and

wherein the third conductive layer is electrically connected to the memory element through the circuit.

17. The semiconductor device according to claim 1,

wherein the memory element is an unerasable memory element.

21. The semiconductor device according to claim 1,

wherein the conductive material is a metal.

5. A semiconductor device comprising a memory element comprising:

a first conductive layer over an insulating surface;

a second conductive layer over the first conductive layer; and

a memory layer interposed between the first conductive layer and the second conductive layer,

wherein the memory layer comprises nanoparticles each of which is coated with an organic thin film,

wherein the nanoparticles comprise a conductive material

wherein the organic thin film comprises a material which forms a coordinate bond with the conductive material, and

wherein the memory element is configured to be written a data by being applied a write voltage to break at least a part of the organic thin film so that at least a part of the nanoparticles contact with each other.

6. The semiconductor device according to claim 5,

wherein grain diameters of the nanoparticles are 1 nm to 200 nm.

7. The semiconductor device according to claim 5,

wherein the memory element is connected to a thin film transistor over a glass substrate or a flexible substrate.

8. The semiconductor device according to claim 5,

wherein the semiconductor device further comprises a third conductive layer serving as an antenna and a circuit comprising a transistor, and

wherein the third conductive layer is electrically connected to the memory element through the circuit.

18. The semiconductor device according to claim 5,

wherein the memory element is an unerasable memory element.

22. The semiconductor device according to claim 5,

wherein the conductive material is a metal.

9. A semiconductor device comprising a memory element comprising:

a first conductive layer over an insulating surface;

a second conductive layer over the first conductive layer;

a memory layer interposed between the first conductive layer and the second conductive layer; and

an insulating layer between the first conductive layer and the memory layer,

wherein the memory layer comprises nanoparticles each of which is coated with an organic thin film,

wherein the nanoparticles comprise a conductive material, and

wherein the memory element is configured to be written a data by being applied a write voltage to break at least a part of the organic thin film so that at least a part of the nanoparticles contact with each other.

10. The semiconductor device according to claim 9,

wherein grain diameters of the nanoparticles are 1 nm to 200 nm.

11. The semiconductor device according to claim 9,

wherein the memory element is connected to a thin film transistor over a glass substrate or a flexible substrate.

12. The semiconductor device according to claim 9,

wherein the semiconductor device further comprises a third conductive layer serving as an antenna and a circuit comprising a transistor, and

wherein the third conductive layer is electrically connected to the memory element through the circuit.

19. The semiconductor device according to claim 9,

wherein the memory element is an unerasable memory element.

23. The semiconductor device according to claim 9,

wherein the conductive material is a metal.

13. A semiconductor device comprising a memory element comprising:

a first conductive layer over an insulating surface;

a second conductive layer over the first conductive layer;

a memory layer interposed between the first conductive layer and the second conductive layer; and

a semiconductor layer between the first conductive layer and the memory layer,

wherein the memory layer comprises nanoparticles each of which is coated with an organic thin film,

wherein the nanoparticles comprise a conductive material, and

wherein the memory element is configured to be written a data by being applied a write voltage to break at least a part of the organic thin film so that at least a part of the nanoparticles contact with each other.

14. The semiconductor device according to claim 13,

wherein grain diameters of the nanoparticles are 1 nm to 200 nm.

15. The semiconductor device according to claim 13,

wherein the memory element is connected to a thin film transistor over a glass substrate or a flexible substrate.

16. The semiconductor device according to claim 13,

wherein the semiconductor device further comprises a third conductive layer serving as an antenna and a circuit comprising a transistor, and

wherein the third conductive layer is electrically connected to the memory element through the circuit.

20. The semiconductor device according to claim 13,

wherein the memory element is an unerasable memory element.

24. The semiconductor device according to claim 15,

wherein the conductive material is a metal.