Staggered oxide semiconductor TFT semiconductor device and manufacturing method thereof

• US 8,841,661 B2
• Filed: 02/05/2010
• Issued: 09/23/2014
• Est. Priority Date: 02/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Akimoto, Kengo, Tsubuku, Masashi
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US12/700,758
• Publication Number:
  US 20100213461A1
• Time in Patent Office: 1,691 Days
• Field of Search: 257/43, 257/57, 257/E29.291
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

A method for forming a thin film transistor includes steps of forming a first wiring layer over a first electrode layer and forming a second wiring layer over a second electrode layer, wherein the first electrode layer extends beyond an end portion of the first wiring layer, the second electrode layer extends beyond an end portion of the second wiring layer, and a semiconductor layer is formed so as to be electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating film over the gate electrode layer;

a first electrode layer and a second electrode layer whose end portions overlap with the gate electrode layer, over the gate insulating film;

a first wiring layer over the first electrode layer;

a second wiring layer over the second electrode layer; and

an oxide semiconductor layer over the gate electrode layer,

wherein the first electrode layer extends beyond an end portion of the first wiring layer,

wherein the second electrode layer extends beyond an end portion of the second wiring layer,

wherein the oxide semiconductor layer is electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer,

wherein the gate insulating film over the gate electrode layer has a region in contact with the oxide semiconductor layer between a region in contact with the first electrode layer and a region in contact with the second electrode layer,

wherein the oxide semiconductor layer is in contact with a side face and a top face of the first wiring layer and a side face and a top face of the second wiring layer, and

wherein the oxide semiconductor layer is in contact with the side face and the top face of the first electrode layer and the side face and the top face of the second electrode layer.

2. The semiconductor device according to claim 1,

wherein a width which is from the end portion of the first electrode layer to the end portion of the first wiring layer or a width which is from the end portion of the second electrode layer to the end portion of the second wiring layer is within the range of from 0.2 μ

m to 5 μ

m, inclusive.

3. The semiconductor device according to claim 1,

wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm, inclusive;

and

wherein a thickness of the first electrode layer or the second electrode layer is within the range of from 5 nm to 200 nm, inclusive.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer is electrically connected to the side face and the top face of the first wiring layer and the side face and the top face of the second wiring layer.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

6. The semiconductor device according to claim 1,

wherein a thickness of the first electrode layer and a thickness of the second electrode layer are smaller than a half of a thickness of the oxide semiconductor layer.

7. A semiconductor device comprising:

a first electrode layer and a second electrode layer;

a first wiring layer over the first electrode layer;

a second wiring layer over the second electrode layer;

an oxide semiconductor layer over the first electrode layer and the second electrode layer;

a gate insulating film over the oxide semiconductor layer; and

a gate electrode layer overlapping with end portions of the first electrode layer and the second electrode layer with the gate insulating film therebetween,

wherein the first electrode layer extends beyond an end portion of the first wiring layer,

wherein the second electrode layer extends beyond an end portion of the second wiring layer,

wherein the oxide semiconductor layer is electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer,

wherein the oxide semiconductor layer is in contact with a side face and a top face of the first wiring layer and a side face and a top face of the second wiring layer, and

wherein the oxide semiconductor layer is in contact with the side face and the top face of the first electrode layer and the side face and the top face of the second electrode layer.

8. The semiconductor device according to claim 7,

wherein a width which is from the end portion of the first electrode layer to the end portion of the first wiring layer or a width which is from the end portion of the second electrode layer to the end portion of the second wiring layer is within the range of from 0.2 μ

m to 5 μ

m, inclusive.

9. The semiconductor device according to claim 7,

wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm, inclusive, and

wherein a thickness of the first electrode layer or the second electrode layer is within the range of from 5 nm to 200 nm, inclusive.

10. The semiconductor device according to claim 7,

wherein the oxide semiconductor layer is electrically connected to the side face and the top face of the first wiring layer and the side face and the top face of the second wiring layer.

11. The semiconductor device according to claim 7,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

12. The semiconductor device according to claim 7,

wherein a thickness of the first electrode layer and a thickness of the second electrode layer are smaller than a half of a thickness of the oxide semiconductor layer.