Wide-gap semiconductor substrate and method to fabricate wide-gap semiconductor device using the same

• US 8,841,681 B2
• Filed: 01/04/2011
• Issued: 09/23/2014
• Est. Priority Date: 07/13/2010
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kuraguchi, Masahiko
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): SPALLA, DAVID C
• Application Number:
  US12/984,106
• Publication Number:
  US 20120012857A1
• Time in Patent Office: 1,358 Days
• Field of Search: 257/76, 257/E21.522, 257/E23.179, 438/14
• US Class Current: 257/76
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/708 Mark formation
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wide-gap semiconductor substrate includes a narrow-gap semiconductor layer, a wide-gap semiconductor layer and an alignment mark. The narrow-gap semiconductor layer has a main surface. The wide-gap semiconductor layer is epitaxially grown on the narrow-gap semiconductor layer. The alignment mark is preliminarily carved in a prescribed position on the main surface so that the alignment mark is preliminarily buried in the wide-gap semiconductor substrate.

Claims

1. A wide-gap semiconductor substrate comprising:

a narrow-gap semiconductor layer having a main surface;

a wide-gap semiconductor layer which is epitaxially grown on the narrow-gap semiconductor layer; and

an alignment mark which is preliminarily carved in a prescribed position on the main surface of the narrow-gap semiconductor layer so that the alignment mark is buried in the wide-gap semiconductor layer,

wherein the narrow-gap semiconductor layer is a Si layer and the wide-gap semiconductor layer includes a nitride semiconductor layer which is made of at least one of a GaN layer and an AlGaN layer,

the main surface of the narrow-gap semiconductor layer, which is not provided with the alignment mark, is fiat, and

a first distance between the main surface of the narrow-gap semiconductor layer and a bottom of the alignment mark is d, a second distance between a main surface of the wide-gap semiconductor laver at a region provided with the alignment mark and the bottom of the alignment mark is 2d or more.

2. A wide-gap semiconductor substrate comprising:

a narrow-gap semiconductor layer having a main surface;

a wide-gap semiconductor layer which is epitaxially grown on the narrow-gap semiconductor layer; and

an alignment mark which is preliminarily carved in a prescribed position on the main surface of the narrow-gap semiconductor laver so that the alignment mark is buried in the wide-gap semiconductor substrate,

wherein the narrow-gap semiconductor layer is a Si layer and the wide-gap semiconductor layer includes a nitride semiconductor layer which is made of at least one of a GaN layer and an AlGaN layer,

the main surface of the narrow-gap semiconductor layer, which is not provided with the alignment mark, is flat, and

a first distance between the main surface of the narrow-gap semiconductor laver and a bottom of the alignment mark is d, a second distance between a main surface of the wide-gap semiconductor layer at a region provided with the alignment mark and the bottom of the alignment mark is 2d or more.

3. A method to fabricate a wide gap semiconductor device on a wide-gap semiconductor substrate, comprising:

applying resist to the wide-gap semiconductor substrate, the wide-gap semiconductor substrate including;

a narrow-gap semiconductor layer having a main surface;

a wide-gap semiconductor layer which is epitaxially grown on the narrow-gap semiconductor layer; and

an alignment mark which is preliminarily carved in a prescribed position on the main surface of the narrow-gap semiconductor layer so that the alignment mark is buried in the wide-gap semiconductor substrate,

wherein the main surface of the narrow-gap semiconductor laver, which is not provided with the alignment mark, is fiat, and

a first distance between the main surface of the narrow-gap semiconductor layer and a bottom of the alignment mark is d, a second distance between a main surface of the wide-gap semiconductor laver at a region provided with the alignment mark and the bottom of the alignment mark is 2d or more, and

irradiating the alignment mark with visible light and detecting light reflected from the alignment mark to align the wide-gap semiconductor substrate; and

detecting a position of the wide-gap semiconductor device using the alignment mark and forming an electrode on the wide-gap semiconductor layer,

wherein the narrow-gap semiconductor layer is a Si layer and the wide-gap semiconductor layer is made of at least one of a GaN layer and an AlGaN layer.

4. The method according to claim 3, wherein

the wide-gap semiconductor device includes a field-effect transistor;

and

the alignment mark is irradiated with visible light and light reflected therefrom is detected to determine positions of a drain, a source and a gate of the field-effect transistor.