Retrograde substrate for deep trench capacitors

• US 8,841,716 B2
• Filed: 07/08/2013
• Issued: 09/23/2014
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Haensch, Wilfried E., Leobandung, Effendi, Yamashita, Tenko, Yeh, Chun-Chen
• Primary Examiner(s): Geyer, Scott B
• Assistant Examiner(s): Seven, Evren
• Application Number:
  US13/936,679
• Publication Number:
  US 20130307121A1
• Time in Patent Office: 442 Days
• Field of Search: None
• US Class Current: 257/305
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H01L 31/112 characterised by field-effect operation, e.g. junction field-effect phototransistor
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.

Claims

1. A semiconductor device, comprising:

a substrate having a buried insulator layer and a first doped portion to a first depth and a second doped portion below the first depth;

a deep trench capacitor formed in the substrate and extending below the first depth, the deep trench capacitor having a buried plate, the buried plate including a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion; and

a well formed in the first doped portion under the buried insulator layer and above the first depth, wherein the well is not in contact with the deep trench capacitor and wherein the well comprises at least one device formed in the well.

2. The semiconductor device as recited in claim 1, wherein the first doped portion includes a p−

type doping and the second doped portion includes an n+ type doping.

3. The semiconductor device as recited in claim 2, wherein the buried plate includes an n+ type doping.

4. The semiconductor device as recited in claim 1, wherein the substrate includes a semiconductor-on-insulator substrate having semiconductor material formed on a buried dielectric layer over the substrate, the semiconductor material having an access transistor for the deep trench capacitor formed in the semiconductor material.

5. The semiconductor device as recited in claim 1, wherein the access transistor includes a fin field effect transistor.

6. The semiconductor device as recited in claim 1, wherein the well extends from an upper surface of the first doped portion to a position above the first depth.

7. The semiconductor device as recited in claim 1, wherein the well includes an n−

doping when the first doped portion includes a p−

doping.

8. The semiconductor device as recited in claim 1, wherein the well includes a p+ doping when the first doped portion includes a p−

doping.

9. The semiconductor device as recited in claim 1, further comprising a diode formed in the well.

10. The semiconductor device as recited in claim 1, further comprising a transistor formed in the well.

11. The semiconductor device as recited in claim 1, further comprising a NPN junction formed in the well.

12. A semiconductor device, comprising:

a semiconductor-on-insulator substrate having a bulk substrate, a buried dielectric layer and a semiconductor material, the bulk substrate including a first doped portion to a first depth and a second doped portion below the first depth;

a memory cell comprising an access transistor formed in the semiconductor material and a deep trench capacitor formed in the bulk substrate and extending below the first depth, the deep trench capacitor having a buried plate, the buried plate including a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion; and

a well formed in the first doped portion under the buried dielectric layer, the well having a different dopant type than the first doped portion, wherein the well is not in contact with the deep trench capacitor and wherein the well comprises at least one device formed in the well.

13. The semiconductor device as recited in claim 12, wherein the first doped portion includes a p−

doping and the second doped portion includes n+ doping.

14. The semiconductor device as recited in claim 13, wherein the buried plate includes an n+ doping.

15. The semiconductor device as recited in claim 12, wherein the access transistor includes a fin field effect transistor.

16. The semiconductor device as recited in claim 12, wherein the well extends from an upper surface of the first doped portion to a position above the first depth, and the well includes at least one of a diode or NPN junction formed in the well.

17. The semiconductor device as recited in claim 12, wherein the well includes an n−

doping when the first doped portion includes a p−

doping and includes a p+ doping when the first doped portion includes a p−

doping.